interconnect.h (10152:52c552138ba1) interconnect.h (10234:5cb711fa6176)
1/*****************************************************************************
2 * McPAT
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
1/*****************************************************************************
2 * McPAT
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
5 * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the

--- 7 unchanged lines hidden (view full) ---

20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the

--- 7 unchanged lines hidden (view full) ---

21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 ***************************************************************************/
31
32
33#ifndef __INTERCONNECT_H__
34#define __INTERCONNECT_H__
35
36#include "assert.h"
37#include "basic_circuit.h"
38#include "basic_components.h"
39#include "cacti_interface.h"
40#include "component.h"
41#include "parameter.h"
42#include "subarray.h"
43#include "wire.h"
44
30 *
31 ***************************************************************************/
32
33
34#ifndef __INTERCONNECT_H__
35#define __INTERCONNECT_H__
36
37#include "assert.h"
38#include "basic_circuit.h"
39#include "basic_components.h"
40#include "cacti_interface.h"
41#include "component.h"
42#include "parameter.h"
43#include "subarray.h"
44#include "wire.h"
45
45// leakge power includes entire htree in a bank (when uca_tree == false)
46// leakge power includes only part to one bank when uca_tree == true
46class InterconnectParameters {
47public:
48 double active_ports;
49};
47
50
48class interconnect : public Component
49{
50 public:
51 interconnect(
52 string name_,
53 enum Device_ty device_ty_,
54 double base_w, double base_h, int data_w, double len,
55 const InputParameter *configure_interface, int start_wiring_level_,
56 bool pipelinable_ = false,
57 double route_over_perc_ =0.5,
58 bool opt_local_=true,
59 enum Core_type core_ty_=Inorder,
60 enum Wire_type wire_model=Global,
61 double width_s=1.0, double space_s=1.0,
62 TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)
63 );
51class InterconnectStatistics {
52public:
53 double duty_cycle;
54 double accesses;
55};
64
56
65 ~interconnect() {};
57class Interconnect : public McPATComponent {
58public:
59 static double width_scaling_threshold;
66
60
67 void compute();
68 string name;
69 enum Device_ty device_ty;
61 enum Device_ty device_ty;
70 double in_rise_time, out_rise_time;
62 double in_rise_time, out_rise_time;
71 InputParameter l_ip;
72 uca_org_t local_result;
63 InputParameter l_ip;
64 uca_org_t local_result;
73 Area no_device_under_wire_area;
65 Area no_device_under_wire_area;
74 void set_in_rise_time(double rt)
75 {
76 in_rise_time = rt;
77 }
78
79 void leakage_feedback(double temperature);
80 double max_unpipelined_link_delay;
81 powerDef power_bit;
82
83 double wire_bw;
66 double max_unpipelined_link_delay;
67 powerDef power_bit;
68
69 double wire_bw;
84 double init_wire_bw; // bus width at root
70 double init_wire_bw;
85 double base_width;
86 double base_height;
87 int data_width;
88 enum Wire_type wt;
89 double width_scaling, space_scaling;
90 int start_wiring_level;
91 double length;
92 double min_w_nmos;
93 double min_w_pmos;
94 double latency, throughput;
71 double base_width;
72 double base_height;
73 int data_width;
74 enum Wire_type wt;
75 double width_scaling, space_scaling;
76 int start_wiring_level;
77 double length;
78 double min_w_nmos;
79 double min_w_pmos;
80 double latency, throughput;
95 bool latency_overflow;
96 bool throughput_overflow;
97 double interconnect_latency;
98 double interconnect_throughput;
81 bool latency_overflow;
82 bool throughput_overflow;
83 double interconnect_latency;
84 double interconnect_throughput;
99 bool opt_local;
100 enum Core_type core_ty;
101 bool pipelinable;
102 double route_over_perc;
85 bool opt_local;
86 enum Core_type core_ty;
87 bool pipelinable;
88 double route_over_perc;
103 int num_pipe_stages;
89 int num_pipe_stages;
90 TechnologyParameter::DeviceType* deviceType;
91 InterconnectParameters int_params;
92 InterconnectStatistics int_stats;
104
93
105 private:
106 TechnologyParameter::DeviceType *deviceType;
107
94 Interconnect(XMLNode* _xml_data, string name_,
95 enum Device_ty device_ty_, double base_w,
96 double base_h, int data_w, double len,
97 const InputParameter *configure_interface,
98 int start_wiring_level_,
99 double _clockRate = 0.0f,
100 bool pipelinable_ = false, double route_over_perc_ = 0.5,
101 bool opt_local_ = true, enum Core_type core_ty_ = Inorder,
102 enum Wire_type wire_model = Global, double width_s = 1.0,
103 double space_s = 1.0,
104 TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
105private:
106 void calcWireData();
107public:
108 void computeArea();
109 void computeEnergy();
110 void set_params_stats(double active_ports,
111 double duty_cycle, double accesses);
112 void leakage_feedback(double temperature);
113 ~Interconnect() {};
108};
109
110#endif
111
114};
115
116#endif
117