4a5
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36c37
< #include "globalvar.h"
---
> #include "basic_components.h"
40,73c41
< interconnect::interconnect(
< string name_,
< enum Device_ty device_ty_,
< double base_w, double base_h,
< int data_w, double len,const InputParameter *configure_interface,
< int start_wiring_level_,
< bool pipelinable_ ,
< double route_over_perc_ ,
< bool opt_local_,
< enum Core_type core_ty_,
< enum Wire_type wire_model,
< double width_s, double space_s,
< TechnologyParameter::DeviceType *dt
< )
< :name(name_),
< device_ty(device_ty_),
< in_rise_time(0),
< out_rise_time(0),
< base_width(base_w),
< base_height(base_h),
< data_width(data_w),
< wt(wire_model),
< width_scaling(width_s),
< space_scaling(space_s),
< start_wiring_level(start_wiring_level_),
< length(len),
< //interconnect_latency(1e-12),
< //interconnect_throughput(1e-12),
< opt_local(opt_local_),
< core_ty(core_ty_),
< pipelinable(pipelinable_),
< route_over_perc(route_over_perc_),
< deviceType(dt)
< {
---
> double Interconnect::width_scaling_threshold = 3.0;
75,77c43,64
< wt = Global;
< l_ip=*configure_interface;
< local_result = init_interface(&l_ip);
---
> Interconnect::Interconnect(XMLNode* _xml_data, string name_,
> enum Device_ty device_ty_, double base_w,
> double base_h, int data_w,
> double len,
> const InputParameter *configure_interface,
> int start_wiring_level_, double _clockRate,
> bool pipelinable_, double route_over_perc_,
> bool opt_local_, enum Core_type core_ty_,
> enum Wire_type wire_model,
> double width_s, double space_s,
> TechnologyParameter::DeviceType *dt)
> : McPATComponent(_xml_data), device_ty(device_ty_), in_rise_time(0),
> out_rise_time(0), base_width(base_w), base_height(base_h),
> data_width(data_w), wt(wire_model), width_scaling(width_s),
> space_scaling(space_s), start_wiring_level(start_wiring_level_),
> length(len), opt_local(opt_local_), core_ty(core_ty_),
> pipelinable(pipelinable_), route_over_perc(route_over_perc_),
> deviceType(dt) {
> name = name_;
> clockRate = _clockRate;
> l_ip = *configure_interface;
> local_result = init_interface(&l_ip, name);
78a66,68
> max_unpipelined_link_delay = 0;
> min_w_nmos = g_tp.min_w_nmos_;
> min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos;
80,82d69
< max_unpipelined_link_delay = 0; //TODO
< min_w_nmos = g_tp.min_w_nmos_;
< min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos;
84a72,75
> latency = l_ip.latency;
> throughput = l_ip.throughput;
> latency_overflow = false;
> throughput_overflow = false;
86,89c77,110
< latency = l_ip.latency;
< throughput = l_ip.throughput;
< latency_overflow=false;
< throughput_overflow=false;
---
> if (pipelinable == false) {
> //Non-pipelinable wires, such as bypass logic, care latency
> calcWireData();
> if (opt_for_clk && opt_local) {
> while (delay > latency &&
> width_scaling < width_scaling_threshold) {
> width_scaling *= 2;
> space_scaling *= 2;
> Wire winit(width_scaling, space_scaling);
> calcWireData();
> }
> if (delay > latency) {
> latency_overflow = true;
> }
> }
> } else {
> //Pipelinable wires, such as bus, does not care latency but throughput
> calcWireData();
> if (opt_for_clk && opt_local) {
> while (delay > throughput &&
> width_scaling < width_scaling_threshold) {
> width_scaling *= 2;
> space_scaling *= 2;
> Wire winit(width_scaling, space_scaling);
> calcWireData();
> }
> if (delay > throughput) {
> // insert pipeline stages
> num_pipe_stages = (int)ceil(delay / throughput);
> assert(num_pipe_stages > 0);
> delay = delay / num_pipe_stages + num_pipe_stages * 0.05 * delay;
> }
> }
> }
91,142c112,117
< /*
< * TODO: Add wiring option from semi-global to global automatically
< * And directly jump to global if semi-global cannot satisfy timing
< * Fat wires only available for global wires, thus
< * if signal wiring layer starts from semi-global,
< * the next layer up will be global, i.e., semi-global does
< * not have fat wires.
< */
< if (pipelinable == false)
< //Non-pipelinable wires, such as bypass logic, care latency
< {
< compute();
< if (opt_for_clk && opt_local)
< {
< while (delay > latency && width_scaling<3.0)
< {
< width_scaling *= 2;
< space_scaling *= 2;
< Wire winit(width_scaling, space_scaling);
< compute();
< }
< if (delay > latency)
< {
< latency_overflow=true;
< }
< }
< }
< else //Pipelinable wires, such as bus, does not care latency but throughput
< {
< /*
< * TODO: Add pipe regs power, area, and timing;
< * Pipelinable wires optimize latency first.
< */
< compute();
< if (opt_for_clk && opt_local)
< {
< while (delay > throughput && width_scaling<3.0)
< {
< width_scaling *= 2;
< space_scaling *= 2;
< Wire winit(width_scaling, space_scaling);
< compute();
< }
< if (delay > throughput)
< // insert pipeline stages
< {
< num_pipe_stages = (int)ceil(delay/throughput);
< assert(num_pipe_stages>0);
< delay = delay/num_pipe_stages + num_pipe_stages*0.05*delay;
< }
< }
< }
---
> power_bit = power;
> power.readOp.dynamic *= data_width;
> power.readOp.leakage *= data_width;
> power.readOp.gate_leakage *= data_width;
> area.set_area(area.get_area()*data_width);
> no_device_under_wire_area.h *= data_width;
144,149c119,122
< power_bit = power;
< power.readOp.dynamic *= data_width;
< power.readOp.leakage *= data_width;
< power.readOp.gate_leakage *= data_width;
< area.set_area(area.get_area()*data_width);
< no_device_under_wire_area.h *= data_width;
---
> if (latency_overflow == true) {
> cout << "Warning: " << name
> << " wire structure cannot satisfy latency constraint." << endl;
> }
151,152c124,126
< if (latency_overflow==true)
< cout<< "Warning: "<< name <<" wire structure cannot satisfy latency constraint." << endl;
---
> assert(power.readOp.dynamic > 0);
> assert(power.readOp.leakage > 0);
> assert(power.readOp.gate_leakage > 0);
153a128,129
> double long_channel_device_reduction =
> longer_channel_device_reduction(device_ty, core_ty);
155,157c131,134
< assert(power.readOp.dynamic > 0);
< assert(power.readOp.leakage > 0);
< assert(power.readOp.gate_leakage > 0);
---
> double sckRation = g_tp.sckt_co_eff;
> power.readOp.dynamic *= sckRation;
> power.writeOp.dynamic *= sckRation;
> power.searchOp.dynamic *= sckRation;
159c136,137
< double long_channel_device_reduction = longer_channel_device_reduction(device_ty,core_ty);
---
> power.readOp.longer_channel_leakage =
> power.readOp.leakage * long_channel_device_reduction;
161,164c139,143
< double sckRation = g_tp.sckt_co_eff;
< power.readOp.dynamic *= sckRation;
< power.writeOp.dynamic *= sckRation;
< power.searchOp.dynamic *= sckRation;
---
> //Only global wires has the option to choose whether routing over or not
> if (pipelinable)
> area.set_area(area.get_area() * route_over_perc +
> no_device_under_wire_area.get_area() *
> (1 - route_over_perc));
166,167c145,146
< power.readOp.longer_channel_leakage =
< power.readOp.leakage*long_channel_device_reduction;
---
> Wire wreset();
> }
169,170d147
< if (pipelinable)//Only global wires has the option to choose whether routing over or not
< area.set_area(area.get_area()*route_over_perc + no_device_under_wire_area.get_area()*(1-route_over_perc));
172,173d148
< Wire wreset();
< }
174a150,151
> void
> Interconnect::calcWireData() {
175a153,158
> Wire *wtemp1 = 0;
> wtemp1 = new Wire(wt, length, 1, width_scaling, space_scaling);
> delay = wtemp1->delay;
> power.readOp.dynamic = wtemp1->power.readOp.dynamic;
> power.readOp.leakage = wtemp1->power.readOp.leakage;
> power.readOp.gate_leakage = wtemp1->power.readOp.gate_leakage;
176a160,168
> area.set_area(wtemp1->area.get_area());
> no_device_under_wire_area.h = (wtemp1->wire_width + wtemp1->wire_spacing);
> no_device_under_wire_area.w = length;
>
> if (wtemp1)
> delete wtemp1;
>
> }
>
178,179c170,171
< interconnect::compute()
< {
---
> Interconnect::computeEnergy() {
> double pppm_t[4] = {1, 1, 1, 1};
181,186c173,178
< Wire *wtemp1 = 0;
< wtemp1 = new Wire(wt, length, 1, width_scaling, space_scaling);
< delay = wtemp1->delay;
< power.readOp.dynamic = wtemp1->power.readOp.dynamic;
< power.readOp.leakage = wtemp1->power.readOp.leakage;
< power.readOp.gate_leakage = wtemp1->power.readOp.gate_leakage;
---
> // Compute TDP
> power_t.reset();
> set_pppm(pppm_t, int_params.active_ports * int_stats.duty_cycle,
> int_params.active_ports, int_params.active_ports,
> int_params.active_ports * int_stats.duty_cycle);
> power_t = power * pppm_t;
188,190c180,183
< area.set_area(wtemp1->area.get_area());
< no_device_under_wire_area.h = (wtemp1->wire_width + wtemp1->wire_spacing);
< no_device_under_wire_area.w = length;
---
> rt_power.reset();
> set_pppm(pppm_t, int_stats.accesses, int_params.active_ports,
> int_params.active_ports, int_stats.accesses);
> rt_power = power * pppm_t;
192,193c185,189
< if (wtemp1)
< delete wtemp1;
---
> output_data.peak_dynamic_power = power_t.readOp.dynamic * clockRate;
> output_data.subthreshold_leakage_power = power_t.readOp.leakage;
> output_data.gate_leakage_power = power_t.readOp.gate_leakage;
> output_data.runtime_dynamic_energy = rt_power.readOp.dynamic;
> }
194a191,193
> void
> Interconnect::computeArea() {
> output_data.area = area.get_area() / 1e6;
197,198c196,204
< void interconnect::leakage_feedback(double temperature)
< {
---
> void
> Interconnect::set_params_stats(double active_ports,
> double duty_cycle, double accesses) {
> int_params.active_ports = active_ports;
> int_stats.duty_cycle = duty_cycle;
> int_stats.accesses = accesses;
> }
>
> void Interconnect::leakage_feedback(double temperature) {
200c206
< uca_org_t init_result = init_interface(&l_ip); // init_result is dummy
---
> uca_org_t init_result = init_interface(&l_ip, name); // init_result is dummy
202c208
< compute();
---
> calcWireData();
213c219,220
< double long_channel_device_reduction = longer_channel_device_reduction(device_ty,core_ty);
---
> double long_channel_device_reduction =
> longer_channel_device_reduction(device_ty,core_ty);
220c227,228
< power.readOp.longer_channel_leakage = power.readOp.leakage*long_channel_device_reduction;
---
> power.readOp.longer_channel_leakage =
> power.readOp.leakage*long_channel_device_reduction;
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36c37
< #include "globalvar.h"
---
> #include "basic_components.h"
40,73c41
< interconnect::interconnect(
< string name_,
< enum Device_ty device_ty_,
< double base_w, double base_h,
< int data_w, double len,const InputParameter *configure_interface,
< int start_wiring_level_,
< bool pipelinable_ ,
< double route_over_perc_ ,
< bool opt_local_,
< enum Core_type core_ty_,
< enum Wire_type wire_model,
< double width_s, double space_s,
< TechnologyParameter::DeviceType *dt
< )
< :name(name_),
< device_ty(device_ty_),
< in_rise_time(0),
< out_rise_time(0),
< base_width(base_w),
< base_height(base_h),
< data_width(data_w),
< wt(wire_model),
< width_scaling(width_s),
< space_scaling(space_s),
< start_wiring_level(start_wiring_level_),
< length(len),
< //interconnect_latency(1e-12),
< //interconnect_throughput(1e-12),
< opt_local(opt_local_),
< core_ty(core_ty_),
< pipelinable(pipelinable_),
< route_over_perc(route_over_perc_),
< deviceType(dt)
< {
---
> double Interconnect::width_scaling_threshold = 3.0;
75,77c43,64
< wt = Global;
< l_ip=*configure_interface;
< local_result = init_interface(&l_ip);
---
> Interconnect::Interconnect(XMLNode* _xml_data, string name_,
> enum Device_ty device_ty_, double base_w,
> double base_h, int data_w,
> double len,
> const InputParameter *configure_interface,
> int start_wiring_level_, double _clockRate,
> bool pipelinable_, double route_over_perc_,
> bool opt_local_, enum Core_type core_ty_,
> enum Wire_type wire_model,
> double width_s, double space_s,
> TechnologyParameter::DeviceType *dt)
> : McPATComponent(_xml_data), device_ty(device_ty_), in_rise_time(0),
> out_rise_time(0), base_width(base_w), base_height(base_h),
> data_width(data_w), wt(wire_model), width_scaling(width_s),
> space_scaling(space_s), start_wiring_level(start_wiring_level_),
> length(len), opt_local(opt_local_), core_ty(core_ty_),
> pipelinable(pipelinable_), route_over_perc(route_over_perc_),
> deviceType(dt) {
> name = name_;
> clockRate = _clockRate;
> l_ip = *configure_interface;
> local_result = init_interface(&l_ip, name);
78a66,68
> max_unpipelined_link_delay = 0;
> min_w_nmos = g_tp.min_w_nmos_;
> min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos;
80,82d69
< max_unpipelined_link_delay = 0; //TODO
< min_w_nmos = g_tp.min_w_nmos_;
< min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos;
84a72,75
> latency = l_ip.latency;
> throughput = l_ip.throughput;
> latency_overflow = false;
> throughput_overflow = false;
86,89c77,110
< latency = l_ip.latency;
< throughput = l_ip.throughput;
< latency_overflow=false;
< throughput_overflow=false;
---
> if (pipelinable == false) {
> //Non-pipelinable wires, such as bypass logic, care latency
> calcWireData();
> if (opt_for_clk && opt_local) {
> while (delay > latency &&
> width_scaling < width_scaling_threshold) {
> width_scaling *= 2;
> space_scaling *= 2;
> Wire winit(width_scaling, space_scaling);
> calcWireData();
> }
> if (delay > latency) {
> latency_overflow = true;
> }
> }
> } else {
> //Pipelinable wires, such as bus, does not care latency but throughput
> calcWireData();
> if (opt_for_clk && opt_local) {
> while (delay > throughput &&
> width_scaling < width_scaling_threshold) {
> width_scaling *= 2;
> space_scaling *= 2;
> Wire winit(width_scaling, space_scaling);
> calcWireData();
> }
> if (delay > throughput) {
> // insert pipeline stages
> num_pipe_stages = (int)ceil(delay / throughput);
> assert(num_pipe_stages > 0);
> delay = delay / num_pipe_stages + num_pipe_stages * 0.05 * delay;
> }
> }
> }
91,142c112,117
< /*
< * TODO: Add wiring option from semi-global to global automatically
< * And directly jump to global if semi-global cannot satisfy timing
< * Fat wires only available for global wires, thus
< * if signal wiring layer starts from semi-global,
< * the next layer up will be global, i.e., semi-global does
< * not have fat wires.
< */
< if (pipelinable == false)
< //Non-pipelinable wires, such as bypass logic, care latency
< {
< compute();
< if (opt_for_clk && opt_local)
< {
< while (delay > latency && width_scaling<3.0)
< {
< width_scaling *= 2;
< space_scaling *= 2;
< Wire winit(width_scaling, space_scaling);
< compute();
< }
< if (delay > latency)
< {
< latency_overflow=true;
< }
< }
< }
< else //Pipelinable wires, such as bus, does not care latency but throughput
< {
< /*
< * TODO: Add pipe regs power, area, and timing;
< * Pipelinable wires optimize latency first.
< */
< compute();
< if (opt_for_clk && opt_local)
< {
< while (delay > throughput && width_scaling<3.0)
< {
< width_scaling *= 2;
< space_scaling *= 2;
< Wire winit(width_scaling, space_scaling);
< compute();
< }
< if (delay > throughput)
< // insert pipeline stages
< {
< num_pipe_stages = (int)ceil(delay/throughput);
< assert(num_pipe_stages>0);
< delay = delay/num_pipe_stages + num_pipe_stages*0.05*delay;
< }
< }
< }
---
> power_bit = power;
> power.readOp.dynamic *= data_width;
> power.readOp.leakage *= data_width;
> power.readOp.gate_leakage *= data_width;
> area.set_area(area.get_area()*data_width);
> no_device_under_wire_area.h *= data_width;
144,149c119,122
< power_bit = power;
< power.readOp.dynamic *= data_width;
< power.readOp.leakage *= data_width;
< power.readOp.gate_leakage *= data_width;
< area.set_area(area.get_area()*data_width);
< no_device_under_wire_area.h *= data_width;
---
> if (latency_overflow == true) {
> cout << "Warning: " << name
> << " wire structure cannot satisfy latency constraint." << endl;
> }
151,152c124,126
< if (latency_overflow==true)
< cout<< "Warning: "<< name <<" wire structure cannot satisfy latency constraint." << endl;
---
> assert(power.readOp.dynamic > 0);
> assert(power.readOp.leakage > 0);
> assert(power.readOp.gate_leakage > 0);
153a128,129
> double long_channel_device_reduction =
> longer_channel_device_reduction(device_ty, core_ty);
155,157c131,134
< assert(power.readOp.dynamic > 0);
< assert(power.readOp.leakage > 0);
< assert(power.readOp.gate_leakage > 0);
---
> double sckRation = g_tp.sckt_co_eff;
> power.readOp.dynamic *= sckRation;
> power.writeOp.dynamic *= sckRation;
> power.searchOp.dynamic *= sckRation;
159c136,137
< double long_channel_device_reduction = longer_channel_device_reduction(device_ty,core_ty);
---
> power.readOp.longer_channel_leakage =
> power.readOp.leakage * long_channel_device_reduction;
161,164c139,143
< double sckRation = g_tp.sckt_co_eff;
< power.readOp.dynamic *= sckRation;
< power.writeOp.dynamic *= sckRation;
< power.searchOp.dynamic *= sckRation;
---
> //Only global wires has the option to choose whether routing over or not
> if (pipelinable)
> area.set_area(area.get_area() * route_over_perc +
> no_device_under_wire_area.get_area() *
> (1 - route_over_perc));
166,167c145,146
< power.readOp.longer_channel_leakage =
< power.readOp.leakage*long_channel_device_reduction;
---
> Wire wreset();
> }
169,170d147
< if (pipelinable)//Only global wires has the option to choose whether routing over or not
< area.set_area(area.get_area()*route_over_perc + no_device_under_wire_area.get_area()*(1-route_over_perc));
172,173d148
< Wire wreset();
< }
174a150,151
> void
> Interconnect::calcWireData() {
175a153,158
> Wire *wtemp1 = 0;
> wtemp1 = new Wire(wt, length, 1, width_scaling, space_scaling);
> delay = wtemp1->delay;
> power.readOp.dynamic = wtemp1->power.readOp.dynamic;
> power.readOp.leakage = wtemp1->power.readOp.leakage;
> power.readOp.gate_leakage = wtemp1->power.readOp.gate_leakage;
176a160,168
> area.set_area(wtemp1->area.get_area());
> no_device_under_wire_area.h = (wtemp1->wire_width + wtemp1->wire_spacing);
> no_device_under_wire_area.w = length;
>
> if (wtemp1)
> delete wtemp1;
>
> }
>
178,179c170,171
< interconnect::compute()
< {
---
> Interconnect::computeEnergy() {
> double pppm_t[4] = {1, 1, 1, 1};
181,186c173,178
< Wire *wtemp1 = 0;
< wtemp1 = new Wire(wt, length, 1, width_scaling, space_scaling);
< delay = wtemp1->delay;
< power.readOp.dynamic = wtemp1->power.readOp.dynamic;
< power.readOp.leakage = wtemp1->power.readOp.leakage;
< power.readOp.gate_leakage = wtemp1->power.readOp.gate_leakage;
---
> // Compute TDP
> power_t.reset();
> set_pppm(pppm_t, int_params.active_ports * int_stats.duty_cycle,
> int_params.active_ports, int_params.active_ports,
> int_params.active_ports * int_stats.duty_cycle);
> power_t = power * pppm_t;
188,190c180,183
< area.set_area(wtemp1->area.get_area());
< no_device_under_wire_area.h = (wtemp1->wire_width + wtemp1->wire_spacing);
< no_device_under_wire_area.w = length;
---
> rt_power.reset();
> set_pppm(pppm_t, int_stats.accesses, int_params.active_ports,
> int_params.active_ports, int_stats.accesses);
> rt_power = power * pppm_t;
192,193c185,189
< if (wtemp1)
< delete wtemp1;
---
> output_data.peak_dynamic_power = power_t.readOp.dynamic * clockRate;
> output_data.subthreshold_leakage_power = power_t.readOp.leakage;
> output_data.gate_leakage_power = power_t.readOp.gate_leakage;
> output_data.runtime_dynamic_energy = rt_power.readOp.dynamic;
> }
194a191,193
> void
> Interconnect::computeArea() {
> output_data.area = area.get_area() / 1e6;
197,198c196,204
< void interconnect::leakage_feedback(double temperature)
< {
---
> void
> Interconnect::set_params_stats(double active_ports,
> double duty_cycle, double accesses) {
> int_params.active_ports = active_ports;
> int_stats.duty_cycle = duty_cycle;
> int_stats.accesses = accesses;
> }
>
> void Interconnect::leakage_feedback(double temperature) {
200c206
< uca_org_t init_result = init_interface(&l_ip); // init_result is dummy
---
> uca_org_t init_result = init_interface(&l_ip, name); // init_result is dummy
202c208
< compute();
---
> calcWireData();
213c219,220
< double long_channel_device_reduction = longer_channel_device_reduction(device_ty,core_ty);
---
> double long_channel_device_reduction =
> longer_channel_device_reduction(device_ty,core_ty);
220c227,228
< power.readOp.longer_channel_leakage = power.readOp.leakage*long_channel_device_reduction;
---
> power.readOp.longer_channel_leakage =
> power.readOp.leakage*long_channel_device_reduction;