1/***************************************************************************** 2 * McPAT 3 * SOFTWARE LICENSE AGREEMENT 4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
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5 * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. |
6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer; 12 * redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution; 15 * neither the name of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
30 * 31 ***************************************************************************/ 32 33 34#ifndef CORE_H_ 35#define CORE_H_ 36
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36#include "XML_Parse.h"
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37#include "array.h" 38#include "basic_components.h"
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39#include "cacheunit.h" |
40#include "interconnect.h" 41#include "logic.h" 42#include "parameter.h"
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42#include "sharedcache.h"
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43
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44class BranchPredictor :public Component {
45 public:
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44// Macros used in the various core-related classes 45#define NUM_SOURCE_OPERANDS 2 46#define NUM_INT_INST_SOURCE_OPERANDS 2 |
47
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47 ParseXML *XML;
48 int ithCore;
49 InputParameter interface_ip;
50 CoreDynParam coredynp;
51 double clockRate,executionTime;
52 double scktRatio, chip_PR_overhead, macro_PR_overhead;
53 ArrayST * globalBPT;
54 ArrayST * localBPT;
55 ArrayST * L1_localBPT;
56 ArrayST * L2_localBPT;
57 ArrayST * chooser;
58 ArrayST * RAS;
59 bool exist;
60
61 BranchPredictor(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
62 void computeEnergy(bool is_tdp=true);
63 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
64 ~BranchPredictor();
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48class BranchPredictorParameters { 49public: 50 int assoc; 51 int nbanks; 52 int local_l1_predictor_size; 53 int local_l2_predictor_size; 54 int local_predictor_entries; 55 int global_predictor_bits; 56 int global_predictor_entries; 57 int chooser_predictor_bits; 58 int chooser_predictor_entries; |
59}; 60
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61class BranchPredictor : public McPATComponent { 62public: 63 ArrayST* globalBPT; 64 ArrayST* localBPT; 65 ArrayST* L1_localBPT; 66 ArrayST* L2_localBPT; 67 ArrayST* chooser; 68 ArrayST* RAS; |
69
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68class InstFetchU :public Component {
69 public:
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70 InputParameter interface_ip; 71 CoreParameters core_params; 72 CoreStatistics core_stats; 73 BranchPredictorParameters branch_pred_params; 74 double scktRatio, chip_PR_overhead, macro_PR_overhead; 75 bool exist; |
76
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71 ParseXML *XML;
72 int ithCore;
73 InputParameter interface_ip;
74 CoreDynParam coredynp;
75 double clockRate,executionTime;
76 double scktRatio, chip_PR_overhead, macro_PR_overhead;
77 enum Cache_policy cache_p;
78 InstCache icache;
79 ArrayST * IB;
80 ArrayST * BTB;
81 BranchPredictor * BPT;
82 inst_decoder * ID_inst;
83 inst_decoder * ID_operand;
84 inst_decoder * ID_misc;
85 bool exist;
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77 BranchPredictor(XMLNode* _xml_data, InputParameter* interface_ip_, 78 const CoreParameters & _core_params, 79 const CoreStatistics & _core_stats, 80 bool exsit = true); 81 void set_params_stats(); 82 void computeEnergy(); 83 void displayData(uint32_t indent = 0, int plevel = 100); 84 ~BranchPredictor(); 85}; |
86
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87 InstFetchU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
88 void computeEnergy(bool is_tdp=true);
89 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
90 ~InstFetchU();
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87class InstFetchParameters { 88public: 89 int btb_size; 90 int btb_block_size; 91 int btb_assoc; 92 int btb_num_banks; 93 int btb_latency; 94 int btb_throughput; 95 int btb_rw_ports; |
96}; 97
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98class InstFetchStatistics { 99public: 100 double btb_read_accesses; 101 double btb_write_accesses; 102}; |
103
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94class SchedulerU :public Component {
95 public:
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104class InstFetchU : public McPATComponent { 105public: 106 CacheUnit* icache; 107 ArrayST* IB; 108 ArrayST* BTB; 109 BranchPredictor* BPT; 110 InstructionDecoder* ID_inst; 111 InstructionDecoder* ID_operand; 112 InstructionDecoder* ID_misc; |
113
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97 ParseXML *XML;
98 int ithCore;
99 InputParameter interface_ip;
100 CoreDynParam coredynp;
101 double clockRate,executionTime;
102 double scktRatio, chip_PR_overhead, macro_PR_overhead;
103 double Iw_height, fp_Iw_height,ROB_height;
104 ArrayST * int_inst_window;
105 ArrayST * fp_inst_window;
106 ArrayST * ROB;
107 selection_logic * instruction_selection;
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114 InputParameter interface_ip; 115 CoreParameters core_params; 116 CoreStatistics core_stats; 117 InstFetchParameters inst_fetch_params; 118 InstFetchStatistics inst_fetch_stats; 119 double scktRatio, chip_PR_overhead, macro_PR_overhead; 120 enum Cache_policy cache_p; |
121 bool exist; 122
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110 SchedulerU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
111 void computeEnergy(bool is_tdp=true);
112 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
113 ~SchedulerU();
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123 InstFetchU(XMLNode* _xml_data, InputParameter* interface_ip_, 124 const CoreParameters & _core_params, 125 const CoreStatistics & _core_stats, 126 bool exsit = true); 127 void set_params_stats(); 128 void computeEnergy(); 129 void displayData(uint32_t indent = 0, int plevel = 100); 130 ~InstFetchU(); |
131}; 132
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116class RENAMINGU :public Component {
117 public:
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133
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119 ParseXML *XML;
120 int ithCore;
121 InputParameter interface_ip;
122 double clockRate,executionTime;
123 CoreDynParam coredynp;
124 ArrayST * iFRAT;
125 ArrayST * fFRAT;
126 ArrayST * iRRAT;
127 ArrayST * fRRAT;
128 ArrayST * ifreeL;
129 ArrayST * ffreeL;
130 dep_resource_conflict_check * idcl;
131 dep_resource_conflict_check * fdcl;
132 ArrayST * RAHT;//register alias history table Used to store GC
133 bool exist;
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134class SchedulerU : public McPATComponent { 135public: 136 static int ROB_STATUS_BITS; |
137
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138 ArrayST* int_inst_window; 139 ArrayST* fp_inst_window; 140 ArrayST* ROB; 141 selection_logic* int_instruction_selection; 142 selection_logic* fp_instruction_selection; |
143
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136 RENAMINGU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_=true);
137 void computeEnergy(bool is_tdp=true);
138 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
139 ~RENAMINGU();
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144 InputParameter interface_ip; 145 CoreParameters core_params; 146 CoreStatistics core_stats; 147 double scktRatio, chip_PR_overhead, macro_PR_overhead; 148 double Iw_height, fp_Iw_height, ROB_height; 149 bool exist; 150 151 SchedulerU(XMLNode* _xml_data, InputParameter* interface_ip_, 152 const CoreParameters & _core_params, 153 const CoreStatistics & _core_stats, 154 bool exist_ = true); 155 void computeEnergy(); 156 void displayData(uint32_t indent = 0, int plevel = 100); 157 ~SchedulerU(); |
158}; 159
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142class LoadStoreU :public Component {
143 public:
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160class RENAMINGU : public McPATComponent { 161public: 162 ArrayST* iFRAT; 163 ArrayST* fFRAT; 164 ArrayST* iRRAT; 165 ArrayST* fRRAT; 166 ArrayST* ifreeL; 167 ArrayST* ffreeL; 168 dep_resource_conflict_check* idcl; 169 dep_resource_conflict_check* fdcl; 170 ArrayST* RAHT; |
171
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145 ParseXML *XML;
146 int ithCore;
147 InputParameter interface_ip;
148 CoreDynParam coredynp;
149 enum Cache_policy cache_p;
150 double clockRate,executionTime;
151 double scktRatio, chip_PR_overhead, macro_PR_overhead;
152 double lsq_height;
153 DataCache dcache;
154 ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
155 ArrayST * LoadQ;
156 bool exist;
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172 InputParameter interface_ip; 173 CoreParameters core_params; 174 CoreStatistics core_stats; 175 bool exist; |
176
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158 LoadStoreU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
159 void computeEnergy(bool is_tdp=true);
160 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
161 ~LoadStoreU();
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177 RENAMINGU(XMLNode* _xml_data, InputParameter* interface_ip_, 178 const CoreParameters & _core_params, 179 const CoreStatistics & _core_stats, 180 bool exist_ = true); 181 void computeEnergy(); 182 void displayData(uint32_t indent = 0, int plevel = 100); 183 ~RENAMINGU(); |
184}; 185
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164class MemManU :public Component {
165 public:
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186class LoadStoreU : public McPATComponent { 187public: 188 CacheUnit* dcache; 189 ArrayST* LSQ; 190 ArrayST* LoadQ; |
191
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167 ParseXML *XML;
168 int ithCore;
169 InputParameter interface_ip;
170 CoreDynParam coredynp;
171 double clockRate,executionTime;
172 double scktRatio, chip_PR_overhead, macro_PR_overhead;
173 ArrayST * itlb;
174 ArrayST * dtlb;
175 bool exist;
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192 InputParameter interface_ip; 193 CoreParameters core_params; 194 CoreStatistics core_stats; 195 enum Cache_policy cache_p; 196 double scktRatio, chip_PR_overhead, macro_PR_overhead; 197 double lsq_height; 198 bool exist; |
199
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177 MemManU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
178 void computeEnergy(bool is_tdp=true);
179 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
180 ~MemManU();
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200 LoadStoreU(XMLNode* _xml_data, InputParameter* interface_ip_, 201 const CoreParameters & _core_params, 202 const CoreStatistics & _core_stats, 203 bool exist_ = true); 204 void computeEnergy(); 205 void displayData(uint32_t indent = 0, int plevel = 100); 206 ~LoadStoreU(); |
207}; 208
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183class RegFU :public Component {
184 public:
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209class MemoryManagementParams { 210public: 211 int itlb_number_entries; 212 double itlb_latency; 213 double itlb_throughput; 214 int itlb_assoc; 215 int itlb_nbanks; 216 int dtlb_number_entries; 217 double dtlb_latency; 218 double dtlb_throughput; 219 int dtlb_assoc; 220 int dtlb_nbanks; 221}; |
222
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186 ParseXML *XML;
187 int ithCore;
188 InputParameter interface_ip;
189 CoreDynParam coredynp;
190 double clockRate,executionTime;
191 double scktRatio, chip_PR_overhead, macro_PR_overhead;
192 double int_regfile_height, fp_regfile_height;
193 ArrayST * IRF;
194 ArrayST * FRF;
195 ArrayST * RFWIN;
196 bool exist;
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223class MemoryManagementStats { 224public: 225 double itlb_total_accesses; 226 double itlb_total_misses; 227 double itlb_conflicts; 228 double dtlb_read_accesses; 229 double dtlb_read_misses; 230 double dtlb_write_accesses; 231 double dtlb_write_misses; 232 double dtlb_conflicts; 233}; |
234
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198 RegFU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
199 void computeEnergy(bool is_tdp=true);
200 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
201 ~RegFU();
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235class MemManU : public McPATComponent { 236public: 237 ArrayST* itlb; 238 ArrayST* dtlb; 239 240 InputParameter interface_ip; 241 CoreParameters core_params; 242 CoreStatistics core_stats; 243 MemoryManagementParams mem_man_params; 244 MemoryManagementStats mem_man_stats; 245 double scktRatio, chip_PR_overhead, macro_PR_overhead; 246 bool exist; 247 248 MemManU(XMLNode* _xml_data, InputParameter* interface_ip_, 249 const CoreParameters & _core_params, 250 const CoreStatistics & _core_stats, bool exist_ = true); 251 void set_params_stats(); 252 void computeEnergy(); 253 void displayData(uint32_t indent = 0, int plevel = 100); 254 ~MemManU(); |
255}; 256
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204class EXECU :public Component {
205 public:
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257class RegFU : public McPATComponent { 258public: 259 static int RFWIN_ACCESS_MULTIPLIER; |
260
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207 ParseXML *XML;
208 int ithCore;
209 InputParameter interface_ip;
210 double clockRate,executionTime;
211 double scktRatio, chip_PR_overhead, macro_PR_overhead;
212 double lsq_height;
213 CoreDynParam coredynp;
214 RegFU * rfu;
215 SchedulerU * scheu;
216 FunctionalUnit * fp_u;
217 FunctionalUnit * exeu;
218 FunctionalUnit * mul;
219 interconnect * int_bypass;
220 interconnect * intTagBypass;
221 interconnect * int_mul_bypass;
222 interconnect * intTag_mul_Bypass;
223 interconnect * fp_bypass;
224 interconnect * fpTagBypass;
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261 ArrayST* IRF; 262 ArrayST* FRF; 263 ArrayST* RFWIN; |
264
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226 Component bypass;
227 bool exist;
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265 InputParameter interface_ip; 266 CoreParameters core_params; 267 CoreStatistics core_stats; 268 double scktRatio, chip_PR_overhead, macro_PR_overhead; 269 double int_regfile_height, fp_regfile_height; 270 bool exist; |
271
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229 EXECU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, double lsq_height_,const CoreDynParam & dyn_p_, bool exist_=true);
230 void computeEnergy(bool is_tdp=true);
231 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
232 ~EXECU();
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272 RegFU(XMLNode* _xml_data, 273 InputParameter* interface_ip_, const CoreParameters & _core_params, 274 const CoreStatistics & _core_stats, 275 bool exist_ = true); 276 void computeEnergy(); 277 void displayData(uint32_t indent = 0, int plevel = 100); 278 ~RegFU(); |
279}; 280
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281class EXECU : public McPATComponent { 282public: 283 RegFU* rfu; 284 SchedulerU* scheu; 285 FunctionalUnit* fp_u; 286 FunctionalUnit* exeu; 287 FunctionalUnit* mul; 288 Interconnect* int_bypass; 289 Interconnect* intTagBypass; 290 Interconnect* int_mul_bypass; 291 Interconnect* intTag_mul_Bypass; 292 Interconnect* fp_bypass; 293 Interconnect* fpTagBypass; |
294
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236class Core :public Component {
237 public:
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295 InputParameter interface_ip; 296 double scktRatio, chip_PR_overhead, macro_PR_overhead; 297 double lsq_height; 298 CoreParameters core_params; 299 CoreStatistics core_stats; 300 bool exist; |
301
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239 ParseXML *XML;
240 int ithCore;
241 InputParameter interface_ip;
242 double clockRate,executionTime;
243 double scktRatio, chip_PR_overhead, macro_PR_overhead;
244 InstFetchU * ifu;
245 LoadStoreU * lsu;
246 MemManU * mmu;
247 EXECU * exu;
248 RENAMINGU * rnu;
249 Pipeline * corepipe;
250 UndiffCore * undiffCore;
251 SharedCache * l2cache;
252 CoreDynParam coredynp;
253 //full_decoder inst_decoder;
254 //clock_network clockNetwork;
255 Core(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
256 void set_core_param();
257 void computeEnergy(bool is_tdp=true);
258 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
259 ~Core();
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302 EXECU(XMLNode* _xml_data, InputParameter* interface_ip_, 303 double lsq_height_, const CoreParameters & _core_params, 304 const CoreStatistics & _core_stats, bool exist_ = true); 305 void computeEnergy(); 306 void displayData(uint32_t indent = 0, int plevel = 100); 307 ~EXECU(); |
308}; 309
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310 311class Core : public McPATComponent { 312public: 313 InstFetchU* ifu; 314 LoadStoreU* lsu; 315 MemManU* mmu; 316 EXECU* exu; 317 RENAMINGU* rnu; 318 Pipeline* corepipe; 319 UndiffCore* undiffCore; 320 CacheUnit* l2cache; 321 322 int ithCore; 323 InputParameter interface_ip; 324 double scktRatio, chip_PR_overhead, macro_PR_overhead; 325 CoreParameters core_params; 326 CoreStatistics core_stats; 327 328 // TODO: Migrate component ID handling into the XML data to remove this 329 // ithCore variable 330 Core(XMLNode* _xml_data, int _ithCore, InputParameter* interface_ip_); 331 void initialize_params(); 332 void initialize_stats(); 333 void set_core_param(); 334 void computeEnergy(); 335 ~Core(); 336}; 337 |
338#endif /* CORE_H_ */
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