4a5
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36d36
< #include "XML_Parse.h"
38a39
> #include "cacheunit.h"
42d42
< #include "sharedcache.h"
44,45c44,46
< class BranchPredictor :public Component {
< public:
---
> // Macros used in the various core-related classes
> #define NUM_SOURCE_OPERANDS 2
> #define NUM_INT_INST_SOURCE_OPERANDS 2
47,64c48,58
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< ArrayST * globalBPT;
< ArrayST * localBPT;
< ArrayST * L1_localBPT;
< ArrayST * L2_localBPT;
< ArrayST * chooser;
< ArrayST * RAS;
< bool exist;
<
< BranchPredictor(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~BranchPredictor();
---
> class BranchPredictorParameters {
> public:
> int assoc;
> int nbanks;
> int local_l1_predictor_size;
> int local_l2_predictor_size;
> int local_predictor_entries;
> int global_predictor_bits;
> int global_predictor_entries;
> int chooser_predictor_bits;
> int chooser_predictor_entries;
66a61,68
> class BranchPredictor : public McPATComponent {
> public:
> ArrayST* globalBPT;
> ArrayST* localBPT;
> ArrayST* L1_localBPT;
> ArrayST* L2_localBPT;
> ArrayST* chooser;
> ArrayST* RAS;
68,69c70,75
< class InstFetchU :public Component {
< public:
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> BranchPredictorParameters branch_pred_params;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> bool exist;
71,85c77,85
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< enum Cache_policy cache_p;
< InstCache icache;
< ArrayST * IB;
< ArrayST * BTB;
< BranchPredictor * BPT;
< inst_decoder * ID_inst;
< inst_decoder * ID_operand;
< inst_decoder * ID_misc;
< bool exist;
---
> BranchPredictor(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exsit = true);
> void set_params_stats();
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~BranchPredictor();
> };
87,90c87,95
< InstFetchU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~InstFetchU();
---
> class InstFetchParameters {
> public:
> int btb_size;
> int btb_block_size;
> int btb_assoc;
> int btb_num_banks;
> int btb_latency;
> int btb_throughput;
> int btb_rw_ports;
92a98,102
> class InstFetchStatistics {
> public:
> double btb_read_accesses;
> double btb_write_accesses;
> };
94,95c104,112
< class SchedulerU :public Component {
< public:
---
> class InstFetchU : public McPATComponent {
> public:
> CacheUnit* icache;
> ArrayST* IB;
> ArrayST* BTB;
> BranchPredictor* BPT;
> InstructionDecoder* ID_inst;
> InstructionDecoder* ID_operand;
> InstructionDecoder* ID_misc;
97,107c114,120
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double Iw_height, fp_Iw_height,ROB_height;
< ArrayST * int_inst_window;
< ArrayST * fp_inst_window;
< ArrayST * ROB;
< selection_logic * instruction_selection;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> InstFetchParameters inst_fetch_params;
> InstFetchStatistics inst_fetch_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> enum Cache_policy cache_p;
110,113c123,130
< SchedulerU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~SchedulerU();
---
> InstFetchU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exsit = true);
> void set_params_stats();
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~InstFetchU();
116,117d132
< class RENAMINGU :public Component {
< public:
119,133c134,136
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< double clockRate,executionTime;
< CoreDynParam coredynp;
< ArrayST * iFRAT;
< ArrayST * fFRAT;
< ArrayST * iRRAT;
< ArrayST * fRRAT;
< ArrayST * ifreeL;
< ArrayST * ffreeL;
< dep_resource_conflict_check * idcl;
< dep_resource_conflict_check * fdcl;
< ArrayST * RAHT;//register alias history table Used to store GC
< bool exist;
---
> class SchedulerU : public McPATComponent {
> public:
> static int ROB_STATUS_BITS;
134a138,142
> ArrayST* int_inst_window;
> ArrayST* fp_inst_window;
> ArrayST* ROB;
> selection_logic* int_instruction_selection;
> selection_logic* fp_instruction_selection;
136,139c144,157
< RENAMINGU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~RENAMINGU();
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double Iw_height, fp_Iw_height, ROB_height;
> bool exist;
>
> SchedulerU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~SchedulerU();
142,143c160,170
< class LoadStoreU :public Component {
< public:
---
> class RENAMINGU : public McPATComponent {
> public:
> ArrayST* iFRAT;
> ArrayST* fFRAT;
> ArrayST* iRRAT;
> ArrayST* fRRAT;
> ArrayST* ifreeL;
> ArrayST* ffreeL;
> dep_resource_conflict_check* idcl;
> dep_resource_conflict_check* fdcl;
> ArrayST* RAHT;
145,156c172,175
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< enum Cache_policy cache_p;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double lsq_height;
< DataCache dcache;
< ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
< ArrayST * LoadQ;
< bool exist;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> bool exist;
158,161c177,183
< LoadStoreU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~LoadStoreU();
---
> RENAMINGU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~RENAMINGU();
164,165c186,190
< class MemManU :public Component {
< public:
---
> class LoadStoreU : public McPATComponent {
> public:
> CacheUnit* dcache;
> ArrayST* LSQ;
> ArrayST* LoadQ;
167,175c192,198
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< ArrayST * itlb;
< ArrayST * dtlb;
< bool exist;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> enum Cache_policy cache_p;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double lsq_height;
> bool exist;
177,180c200,206
< MemManU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~MemManU();
---
> LoadStoreU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~LoadStoreU();
183,184c209,221
< class RegFU :public Component {
< public:
---
> class MemoryManagementParams {
> public:
> int itlb_number_entries;
> double itlb_latency;
> double itlb_throughput;
> int itlb_assoc;
> int itlb_nbanks;
> int dtlb_number_entries;
> double dtlb_latency;
> double dtlb_throughput;
> int dtlb_assoc;
> int dtlb_nbanks;
> };
186,196c223,233
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double int_regfile_height, fp_regfile_height;
< ArrayST * IRF;
< ArrayST * FRF;
< ArrayST * RFWIN;
< bool exist;
---
> class MemoryManagementStats {
> public:
> double itlb_total_accesses;
> double itlb_total_misses;
> double itlb_conflicts;
> double dtlb_read_accesses;
> double dtlb_read_misses;
> double dtlb_write_accesses;
> double dtlb_write_misses;
> double dtlb_conflicts;
> };
198,201c235,254
< RegFU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~RegFU();
---
> class MemManU : public McPATComponent {
> public:
> ArrayST* itlb;
> ArrayST* dtlb;
>
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> MemoryManagementParams mem_man_params;
> MemoryManagementStats mem_man_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> bool exist;
>
> MemManU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats, bool exist_ = true);
> void set_params_stats();
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~MemManU();
204,205c257,259
< class EXECU :public Component {
< public:
---
> class RegFU : public McPATComponent {
> public:
> static int RFWIN_ACCESS_MULTIPLIER;
207,224c261,263
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double lsq_height;
< CoreDynParam coredynp;
< RegFU * rfu;
< SchedulerU * scheu;
< FunctionalUnit * fp_u;
< FunctionalUnit * exeu;
< FunctionalUnit * mul;
< interconnect * int_bypass;
< interconnect * intTagBypass;
< interconnect * int_mul_bypass;
< interconnect * intTag_mul_Bypass;
< interconnect * fp_bypass;
< interconnect * fpTagBypass;
---
> ArrayST* IRF;
> ArrayST* FRF;
> ArrayST* RFWIN;
226,227c265,270
< Component bypass;
< bool exist;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double int_regfile_height, fp_regfile_height;
> bool exist;
229,232c272,278
< EXECU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, double lsq_height_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~EXECU();
---
> RegFU(XMLNode* _xml_data,
> InputParameter* interface_ip_, const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~RegFU();
234a281,293
> class EXECU : public McPATComponent {
> public:
> RegFU* rfu;
> SchedulerU* scheu;
> FunctionalUnit* fp_u;
> FunctionalUnit* exeu;
> FunctionalUnit* mul;
> Interconnect* int_bypass;
> Interconnect* intTagBypass;
> Interconnect* int_mul_bypass;
> Interconnect* intTag_mul_Bypass;
> Interconnect* fp_bypass;
> Interconnect* fpTagBypass;
236,237c295,300
< class Core :public Component {
< public:
---
> InputParameter interface_ip;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double lsq_height;
> CoreParameters core_params;
> CoreStatistics core_stats;
> bool exist;
239,259c302,307
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< InstFetchU * ifu;
< LoadStoreU * lsu;
< MemManU * mmu;
< EXECU * exu;
< RENAMINGU * rnu;
< Pipeline * corepipe;
< UndiffCore * undiffCore;
< SharedCache * l2cache;
< CoreDynParam coredynp;
< //full_decoder inst_decoder;
< //clock_network clockNetwork;
< Core(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
< void set_core_param();
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~Core();
---
> EXECU(XMLNode* _xml_data, InputParameter* interface_ip_,
> double lsq_height_, const CoreParameters & _core_params,
> const CoreStatistics & _core_stats, bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~EXECU();
261a310,337
>
> class Core : public McPATComponent {
> public:
> InstFetchU* ifu;
> LoadStoreU* lsu;
> MemManU* mmu;
> EXECU* exu;
> RENAMINGU* rnu;
> Pipeline* corepipe;
> UndiffCore* undiffCore;
> CacheUnit* l2cache;
>
> int ithCore;
> InputParameter interface_ip;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> CoreParameters core_params;
> CoreStatistics core_stats;
>
> // TODO: Migrate component ID handling into the XML data to remove this
> // ithCore variable
> Core(XMLNode* _xml_data, int _ithCore, InputParameter* interface_ip_);
> void initialize_params();
> void initialize_stats();
> void set_core_param();
> void computeEnergy();
> ~Core();
> };
>
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36d36
< #include "XML_Parse.h"
38a39
> #include "cacheunit.h"
42d42
< #include "sharedcache.h"
44,45c44,46
< class BranchPredictor :public Component {
< public:
---
> // Macros used in the various core-related classes
> #define NUM_SOURCE_OPERANDS 2
> #define NUM_INT_INST_SOURCE_OPERANDS 2
47,64c48,58
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< ArrayST * globalBPT;
< ArrayST * localBPT;
< ArrayST * L1_localBPT;
< ArrayST * L2_localBPT;
< ArrayST * chooser;
< ArrayST * RAS;
< bool exist;
<
< BranchPredictor(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~BranchPredictor();
---
> class BranchPredictorParameters {
> public:
> int assoc;
> int nbanks;
> int local_l1_predictor_size;
> int local_l2_predictor_size;
> int local_predictor_entries;
> int global_predictor_bits;
> int global_predictor_entries;
> int chooser_predictor_bits;
> int chooser_predictor_entries;
66a61,68
> class BranchPredictor : public McPATComponent {
> public:
> ArrayST* globalBPT;
> ArrayST* localBPT;
> ArrayST* L1_localBPT;
> ArrayST* L2_localBPT;
> ArrayST* chooser;
> ArrayST* RAS;
68,69c70,75
< class InstFetchU :public Component {
< public:
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> BranchPredictorParameters branch_pred_params;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> bool exist;
71,85c77,85
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< enum Cache_policy cache_p;
< InstCache icache;
< ArrayST * IB;
< ArrayST * BTB;
< BranchPredictor * BPT;
< inst_decoder * ID_inst;
< inst_decoder * ID_operand;
< inst_decoder * ID_misc;
< bool exist;
---
> BranchPredictor(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exsit = true);
> void set_params_stats();
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~BranchPredictor();
> };
87,90c87,95
< InstFetchU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~InstFetchU();
---
> class InstFetchParameters {
> public:
> int btb_size;
> int btb_block_size;
> int btb_assoc;
> int btb_num_banks;
> int btb_latency;
> int btb_throughput;
> int btb_rw_ports;
92a98,102
> class InstFetchStatistics {
> public:
> double btb_read_accesses;
> double btb_write_accesses;
> };
94,95c104,112
< class SchedulerU :public Component {
< public:
---
> class InstFetchU : public McPATComponent {
> public:
> CacheUnit* icache;
> ArrayST* IB;
> ArrayST* BTB;
> BranchPredictor* BPT;
> InstructionDecoder* ID_inst;
> InstructionDecoder* ID_operand;
> InstructionDecoder* ID_misc;
97,107c114,120
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double Iw_height, fp_Iw_height,ROB_height;
< ArrayST * int_inst_window;
< ArrayST * fp_inst_window;
< ArrayST * ROB;
< selection_logic * instruction_selection;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> InstFetchParameters inst_fetch_params;
> InstFetchStatistics inst_fetch_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> enum Cache_policy cache_p;
110,113c123,130
< SchedulerU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~SchedulerU();
---
> InstFetchU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exsit = true);
> void set_params_stats();
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~InstFetchU();
116,117d132
< class RENAMINGU :public Component {
< public:
119,133c134,136
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< double clockRate,executionTime;
< CoreDynParam coredynp;
< ArrayST * iFRAT;
< ArrayST * fFRAT;
< ArrayST * iRRAT;
< ArrayST * fRRAT;
< ArrayST * ifreeL;
< ArrayST * ffreeL;
< dep_resource_conflict_check * idcl;
< dep_resource_conflict_check * fdcl;
< ArrayST * RAHT;//register alias history table Used to store GC
< bool exist;
---
> class SchedulerU : public McPATComponent {
> public:
> static int ROB_STATUS_BITS;
134a138,142
> ArrayST* int_inst_window;
> ArrayST* fp_inst_window;
> ArrayST* ROB;
> selection_logic* int_instruction_selection;
> selection_logic* fp_instruction_selection;
136,139c144,157
< RENAMINGU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~RENAMINGU();
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double Iw_height, fp_Iw_height, ROB_height;
> bool exist;
>
> SchedulerU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~SchedulerU();
142,143c160,170
< class LoadStoreU :public Component {
< public:
---
> class RENAMINGU : public McPATComponent {
> public:
> ArrayST* iFRAT;
> ArrayST* fFRAT;
> ArrayST* iRRAT;
> ArrayST* fRRAT;
> ArrayST* ifreeL;
> ArrayST* ffreeL;
> dep_resource_conflict_check* idcl;
> dep_resource_conflict_check* fdcl;
> ArrayST* RAHT;
145,156c172,175
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< enum Cache_policy cache_p;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double lsq_height;
< DataCache dcache;
< ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
< ArrayST * LoadQ;
< bool exist;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> bool exist;
158,161c177,183
< LoadStoreU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~LoadStoreU();
---
> RENAMINGU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~RENAMINGU();
164,165c186,190
< class MemManU :public Component {
< public:
---
> class LoadStoreU : public McPATComponent {
> public:
> CacheUnit* dcache;
> ArrayST* LSQ;
> ArrayST* LoadQ;
167,175c192,198
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< ArrayST * itlb;
< ArrayST * dtlb;
< bool exist;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> enum Cache_policy cache_p;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double lsq_height;
> bool exist;
177,180c200,206
< MemManU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~MemManU();
---
> LoadStoreU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~LoadStoreU();
183,184c209,221
< class RegFU :public Component {
< public:
---
> class MemoryManagementParams {
> public:
> int itlb_number_entries;
> double itlb_latency;
> double itlb_throughput;
> int itlb_assoc;
> int itlb_nbanks;
> int dtlb_number_entries;
> double dtlb_latency;
> double dtlb_throughput;
> int dtlb_assoc;
> int dtlb_nbanks;
> };
186,196c223,233
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< CoreDynParam coredynp;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double int_regfile_height, fp_regfile_height;
< ArrayST * IRF;
< ArrayST * FRF;
< ArrayST * RFWIN;
< bool exist;
---
> class MemoryManagementStats {
> public:
> double itlb_total_accesses;
> double itlb_total_misses;
> double itlb_conflicts;
> double dtlb_read_accesses;
> double dtlb_read_misses;
> double dtlb_write_accesses;
> double dtlb_write_misses;
> double dtlb_conflicts;
> };
198,201c235,254
< RegFU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~RegFU();
---
> class MemManU : public McPATComponent {
> public:
> ArrayST* itlb;
> ArrayST* dtlb;
>
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> MemoryManagementParams mem_man_params;
> MemoryManagementStats mem_man_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> bool exist;
>
> MemManU(XMLNode* _xml_data, InputParameter* interface_ip_,
> const CoreParameters & _core_params,
> const CoreStatistics & _core_stats, bool exist_ = true);
> void set_params_stats();
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~MemManU();
204,205c257,259
< class EXECU :public Component {
< public:
---
> class RegFU : public McPATComponent {
> public:
> static int RFWIN_ACCESS_MULTIPLIER;
207,224c261,263
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< double lsq_height;
< CoreDynParam coredynp;
< RegFU * rfu;
< SchedulerU * scheu;
< FunctionalUnit * fp_u;
< FunctionalUnit * exeu;
< FunctionalUnit * mul;
< interconnect * int_bypass;
< interconnect * intTagBypass;
< interconnect * int_mul_bypass;
< interconnect * intTag_mul_Bypass;
< interconnect * fp_bypass;
< interconnect * fpTagBypass;
---
> ArrayST* IRF;
> ArrayST* FRF;
> ArrayST* RFWIN;
226,227c265,270
< Component bypass;
< bool exist;
---
> InputParameter interface_ip;
> CoreParameters core_params;
> CoreStatistics core_stats;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double int_regfile_height, fp_regfile_height;
> bool exist;
229,232c272,278
< EXECU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, double lsq_height_,const CoreDynParam & dyn_p_, bool exist_=true);
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~EXECU();
---
> RegFU(XMLNode* _xml_data,
> InputParameter* interface_ip_, const CoreParameters & _core_params,
> const CoreStatistics & _core_stats,
> bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~RegFU();
234a281,293
> class EXECU : public McPATComponent {
> public:
> RegFU* rfu;
> SchedulerU* scheu;
> FunctionalUnit* fp_u;
> FunctionalUnit* exeu;
> FunctionalUnit* mul;
> Interconnect* int_bypass;
> Interconnect* intTagBypass;
> Interconnect* int_mul_bypass;
> Interconnect* intTag_mul_Bypass;
> Interconnect* fp_bypass;
> Interconnect* fpTagBypass;
236,237c295,300
< class Core :public Component {
< public:
---
> InputParameter interface_ip;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> double lsq_height;
> CoreParameters core_params;
> CoreStatistics core_stats;
> bool exist;
239,259c302,307
< ParseXML *XML;
< int ithCore;
< InputParameter interface_ip;
< double clockRate,executionTime;
< double scktRatio, chip_PR_overhead, macro_PR_overhead;
< InstFetchU * ifu;
< LoadStoreU * lsu;
< MemManU * mmu;
< EXECU * exu;
< RENAMINGU * rnu;
< Pipeline * corepipe;
< UndiffCore * undiffCore;
< SharedCache * l2cache;
< CoreDynParam coredynp;
< //full_decoder inst_decoder;
< //clock_network clockNetwork;
< Core(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
< void set_core_param();
< void computeEnergy(bool is_tdp=true);
< void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
< ~Core();
---
> EXECU(XMLNode* _xml_data, InputParameter* interface_ip_,
> double lsq_height_, const CoreParameters & _core_params,
> const CoreStatistics & _core_stats, bool exist_ = true);
> void computeEnergy();
> void displayData(uint32_t indent = 0, int plevel = 100);
> ~EXECU();
261a310,337
>
> class Core : public McPATComponent {
> public:
> InstFetchU* ifu;
> LoadStoreU* lsu;
> MemManU* mmu;
> EXECU* exu;
> RENAMINGU* rnu;
> Pipeline* corepipe;
> UndiffCore* undiffCore;
> CacheUnit* l2cache;
>
> int ithCore;
> InputParameter interface_ip;
> double scktRatio, chip_PR_overhead, macro_PR_overhead;
> CoreParameters core_params;
> CoreStatistics core_stats;
>
> // TODO: Migrate component ID handling into the XML data to remove this
> // ithCore variable
> Core(XMLNode* _xml_data, int _ithCore, InputParameter* interface_ip_);
> void initialize_params();
> void initialize_stats();
> void set_core_param();
> void computeEnergy();
> ~Core();
> };
>