1/*****************************************************************************
2 * McPAT/CACTI
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
5 * All Rights Reserved
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8 * modification, are permitted provided that the following conditions are
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11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
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14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 ***************************************************************************/
31
32
33
34#ifndef __UCA_H__
35#define __UCA_H__
36
37#include "area.h"
38#include "bank.h"
39#include "component.h"
40#include "htree2.h"
41#include "parameter.h"
42
43class UCA : public Component
44{
45 public:
46 UCA(const DynamicParameter & dyn_p);
47 ~UCA();
48 double compute_delays(double inrisetime); // returns outrisetime
49 void compute_power_energy();
50
51 DynamicParameter dp;
52 Bank bank;
53
54 Htree2 * htree_in_add;
55 Htree2 * htree_in_data;
56 Htree2 * htree_out_data;
57 Htree2 * htree_in_search;
58 Htree2 * htree_out_search;
59
60 powerDef power_routing_to_bank;
61
62 uint32_t nbanks;
63
64 int num_addr_b_bank;
65 int num_di_b_bank;
66 int num_do_b_bank;
67 int num_si_b_bank;
68 int num_so_b_bank;
69 int RWP, ERP, EWP,SCHP;
70 double area_all_dataramcells;
71
72 double dyn_read_energy_from_closed_page;
73 double dyn_read_energy_from_open_page;
74 double dyn_read_energy_remaining_words_in_burst;
75
76 double refresh_power; // only for DRAM
77 double activate_energy;
78 double read_energy;
79 double write_energy;
80 double precharge_energy;
81 double leak_power_subbank_closed_page;
82 double leak_power_subbank_open_page;
83 double leak_power_request_and_reply_networks;
84
85 double delay_array_to_sa_mux_lev_1_decoder;
86 double delay_array_to_sa_mux_lev_2_decoder;
87 double delay_before_subarray_output_driver;
88 double delay_from_subarray_out_drv_to_out;
89 double access_time;
90 double precharge_delay;
91 double multisubbank_interleave_cycle_time;
92};
93
94#endif
95