htree2.h (10152:52c552138ba1) htree2.h (10234:5cb711fa6176)
1/*****************************************************************************
2 * McPAT/CACTI
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
1/*****************************************************************************
2 * McPAT/CACTI
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
5 * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the

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20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the

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21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 ***************************************************************************/
31
32
33#ifndef __HTREE2_H__
34#define __HTREE2_H__
35
36#include "assert.h"
37#include "basic_circuit.h"
38#include "cacti_interface.h"
39#include "component.h"
40#include "parameter.h"
41#include "subarray.h"
42#include "wire.h"
43
44// leakge power includes entire htree in a bank (when uca_tree == false)
45// leakge power includes only part to one bank when uca_tree == true
46
30 *
31 ***************************************************************************/
32
33
34#ifndef __HTREE2_H__
35#define __HTREE2_H__
36
37#include "assert.h"
38#include "basic_circuit.h"
39#include "cacti_interface.h"
40#include "component.h"
41#include "parameter.h"
42#include "subarray.h"
43#include "wire.h"
44
45// leakge power includes entire htree in a bank (when uca_tree == false)
46// leakge power includes only part to one bank when uca_tree == true
47
47class Htree2 : public Component
48{
49 public:
48class Htree2 : public Component {
49public:
50 Htree2(enum Wire_type wire_model,
50 Htree2(enum Wire_type wire_model,
51 double mat_w, double mat_h, int add, int data_in, int search_data_in, int data_out, int search_data_out, int bl, int wl,
52 enum Htree_type h_type, bool uca_tree_ = false, bool search_tree_ = false,
53 TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
51 double mat_w, double mat_h, int add, int data_in, int search_data_in, int data_out, int search_data_out, int bl, int wl,
52 enum Htree_type h_type, bool uca_tree_ = false, bool search_tree_ = false,
53 TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
54 ~Htree2() {};
55
56 void in_htree();
57 void out_htree();
58
59 // repeaters only at h-tree nodes
60 void limited_in_htree();
61 void limited_out_htree();
62 void input_nand(double s1, double s2, double l);
63 void output_buffer(double s1, double s2, double l);
64
65 double in_rise_time, out_rise_time;
66
54 ~Htree2() {};
55
56 void in_htree();
57 void out_htree();
58
59 // repeaters only at h-tree nodes
60 void limited_in_htree();
61 void limited_out_htree();
62 void input_nand(double s1, double s2, double l);
63 void output_buffer(double s1, double s2, double l);
64
65 double in_rise_time, out_rise_time;
66
67 void set_in_rise_time(double rt)
68 {
69 in_rise_time = rt;
67 void set_in_rise_time(double rt) {
68 in_rise_time = rt;
70 }
71
72 double max_unpipelined_link_delay;
73 powerDef power_bit;
74
75
69 }
70
71 double max_unpipelined_link_delay;
72 powerDef power_bit;
73
74
76 private:
75private:
77 double wire_bw;
78 double init_wire_bw; // bus width at root
79 enum Htree_type tree_type;
80 double htree_hnodes;
81 double htree_vnodes;
82 double mat_width;
83 double mat_height;
76 double wire_bw;
77 double init_wire_bw; // bus width at root
78 enum Htree_type tree_type;
79 double htree_hnodes;
80 double htree_vnodes;
81 double mat_width;
82 double mat_height;
84 int add_bits, data_in_bits,search_data_in_bits,data_out_bits, search_data_out_bits;
83 int add_bits;
84 int data_in_bits;
85 int search_data_in_bits;
86 int data_out_bits;
87 int search_data_out_bits;
85 int ndbl, ndwl;
86 bool uca_tree; // should have full bandwidth to access all banks in the array simultaneously
87 bool search_tree;
88
89 enum Wire_type wt;
90 double min_w_nmos;
91 double min_w_pmos;
92
93 TechnologyParameter::DeviceType *deviceType;
94
95};
96
97#endif
88 int ndbl, ndwl;
89 bool uca_tree; // should have full bandwidth to access all banks in the array simultaneously
90 bool search_tree;
91
92 enum Wire_type wt;
93 double min_w_nmos;
94 double min_w_pmos;
95
96 TechnologyParameter::DeviceType *deviceType;
97
98};
99
100#endif