1/*****************************************************************************
2 * McPAT/CACTI
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
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9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 ***************************************************************************/
31
32
33
34#ifndef __BASIC_CIRCUIT_H__
35#define __BASIC_CIRCUIT_H__
36
37#include "cacti_interface.h"
38#include "const.h"
39
40using namespace std;
41
42#define UNI_LEAK_STACK_FACTOR 0.43
43
44int powers (int base, int n);
45bool is_pow2(int64_t val);
46uint32_t _log2(uint64_t num);
47int factorial(int n, int m = 1);
48int combination(int n, int m);
49
50//#define DBG
51#ifdef DBG
52 #define PRINTDW(a);\
53 a;
54#else
55 #define PRINTDW(a);\
56
57#endif
58
59
60enum Wire_placement {
61 outside_mat,
62 inside_mat,
63 local_wires
64};
65
66
67
68enum Htree_type {
69 Add_htree,
70 Data_in_htree,
71 Data_out_htree,
72 Search_in_htree,
73 Search_out_htree,
74};
75
76enum Gate_type {
77 nmos,
78 pmos,
79 inv,
80 nand,
81 nor,
82 tri,
83 tg
84};
85
86enum Half_net_topology {
87 parallel,
88 series
89};
90
91double logtwo (double x);
92
93double gate_C(
94 double width,
95 double wirelength,
96 bool _is_dram = false,
97 bool _is_sram = false,
98 bool _is_wl_tr = false);
99
100double gate_C_pass(
101 double width,
102 double wirelength,
103 bool _is_dram = false,
104 bool _is_sram = false,
105 bool _is_wl_tr = false);
106
107double drain_C_(
108 double width,
109 int nchannel,
110 int stack,
111 int next_arg_thresh_folding_width_or_height_cell,
112 double fold_dimension,
113 bool _is_dram = false,
114 bool _is_sram = false,
115 bool _is_wl_tr = false);
116
117double tr_R_on(
118 double width,
119 int nchannel,
120 int stack,
121 bool _is_dram = false,
122 bool _is_sram = false,
123 bool _is_wl_tr = false);
124
125double R_to_w(
126 double res,
127 int nchannel,
128 bool _is_dram = false,
129 bool _is_sram = false,
130 bool _is_wl_tr = false);
131
132double horowitz (
133 double inputramptime,
134 double tf,
135 double vs1,
136 double vs2,
137 int rise);
138
139double pmos_to_nmos_sz_ratio(
140 bool _is_dram = false,
141 bool _is_wl_tr = false);
142
143double simplified_nmos_leakage(
144 double nwidth,
145 bool _is_dram = false,
146 bool _is_cell = false,
147 bool _is_wl_tr = false);
148
149double simplified_pmos_leakage(
150 double pwidth,
151 bool _is_dram = false,
152 bool _is_cell = false,
153 bool _is_wl_tr = false);
154
155
156double cmos_Ileak(
157 double nWidth,
158 double pWidth,
159 bool _is_dram = false,
160 bool _is_cell = false,
161 bool _is_wl_tr = false);
162
163double cmos_Ig_n(
164 double nWidth,
165 bool _is_dram = false,
166 bool _is_cell = false,
167 bool _is_wl_tr= false);
168
169double cmos_Ig_p(
170 double pWidth,
171 bool _is_dram = false,
172 bool _is_cell = false,
173 bool _is_wl_tr= false);
174
175
176double cmos_Isub_leakage(
177 double nWidth,
178 double pWidth,
179 int fanin,
180 enum Gate_type g_type,
181 bool _is_dram = false,
182 bool _is_cell = false,
183 bool _is_wl_tr = false,
184 enum Half_net_topology topo = series);
185
186double cmos_Ig_leakage(
187 double nWidth,
188 double pWidth,
189 int fanin,
190 enum Gate_type g_type,
191 bool _is_dram = false,
192 bool _is_cell = false,
193 bool _is_wl_tr = false,
194 enum Half_net_topology topo = series);
195
196double shortcircuit(
197 double vt,
198 double velocity_index,
199 double c_in,
200 double c_out,
201 double w_nmos,
202 double w_pmos,
203 double i_on_n,
204 double i_on_p,
205 double i_on_n_in,
206 double i_on_p_in,
207 double vdd);
208
209double shortcircuit_simple(
210 double vt,
211 double velocity_index,
212 double c_in,
213 double c_out,
214 double w_nmos,
215 double w_pmos,
216 double i_on_n,
217 double i_on_p,
218 double i_on_n_in,
219 double i_on_p_in,
220 double vdd);
221//set power point product mask; strictly speaking this is not real point product
222inline void set_pppm(
223 double * pppv,
224 double a=1,
225 double b=1,
226 double c=1,
227 double d=1
228 ){
229 pppv[0]= a;
230 pppv[1]= b;
231 pppv[2]= c;
232 pppv[3]= d;
233
234}
235
236inline void set_sppm(
237 double * sppv,
238 double a=1,
239 double b=1,
240 double c=1,
241 double d=1
242 ){
243 sppv[0]= a;
244 sppv[1]= b;
245 sppv[2]= c;
246}
247
248#endif