4a5
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42,44c43,44
< uint32_t _log2(uint64_t num)
< {
< uint32_t log2 = 0;
---
> uint32_t _log2(uint64_t num) {
> uint32_t log2 = 0;
46,50c46,49
< if (num == 0)
< {
< std::cerr << "log0?" << std::endl;
< exit(1);
< }
---
> if (num == 0) {
> std::cerr << "log0?" << std::endl;
> exit(1);
> }
52,56c51,54
< while (num > 1)
< {
< num = (num >> 1);
< log2++;
< }
---
> while (num > 1) {
> num = (num >> 1);
> log2++;
> }
58c56
< return log2;
---
> return log2;
62,75c60,67
< bool is_pow2(int64_t val)
< {
< if (val <= 0)
< {
< return false;
< }
< else if (val == 1)
< {
< return true;
< }
< else
< {
< return (_log2(val) != _log2(val-1));
< }
---
> bool is_pow2(int64_t val) {
> if (val <= 0) {
> return false;
> } else if (val == 1) {
> return true;
> } else {
> return (_log2(val) != _log2(val - 1));
> }
79,81c71,72
< int powers (int base, int n)
< {
< int i, p;
---
> int powers (int base, int n) {
> int i, p;
83,86c74,77
< p = 1;
< for (i = 1; i <= n; ++i)
< p *= base;
< return p;
---
> p = 1;
> for (i = 1; i <= n; ++i)
> p *= base;
> return p;
91,94c82,84
< double logtwo (double x)
< {
< assert(x > 0);
< return ((double) (log (x) / log (2.0)));
---
> double logtwo (double x) {
> assert(x > 0);
> return ((double) (log (x) / log (2.0)));
105,107c95,96
< bool _is_wl_tr)
< {
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> const TechnologyParameter::DeviceType * dt;
109,124c98,106
< if (_is_dram && _is_cell)
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if (_is_dram && _is_wl_tr)
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if (!_is_dram && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if (_is_dram && _is_cell) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if (_is_dram && _is_wl_tr) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if (!_is_dram && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
126c108
< return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
---
> return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
137,140c119,121
< bool _is_wl_tr)
< {
< // v5.0
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> // v5.0
> const TechnologyParameter::DeviceType * dt;
142,157c123,131
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if ((!_is_dram) && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if ((!_is_dram) && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
159c133
< return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
---
> return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
172,175c146,148
< bool _is_wl_tr)
< {
< double w_folded_tr;
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> double w_folded_tr;
> const TechnologyParameter::DeviceType * dt;
177,192c150,158
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; // DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; // DRAM wordline transistor
< }
< else if ((!_is_dram) && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; // DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; // DRAM wordline transistor
> } else if ((!_is_dram) && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
194,198c160,164
< double c_junc_area = dt->C_junc;
< double c_junc_sidewall = dt->C_junc_sidewall;
< double c_fringe = 2*dt->C_fringe;
< double c_overlap = 2*dt->C_overlap;
< double drain_C_metal_connecting_folded_tr = 0;
---
> double c_junc_area = dt->C_junc;
> double c_junc_sidewall = dt->C_junc_sidewall;
> double c_fringe = 2 * dt->C_fringe;
> double c_overlap = 2 * dt->C_overlap;
> double drain_C_metal_connecting_folded_tr = 0;
200,213c166,179
< // determine the width of the transistor after folding (if it is getting folded)
< if (next_arg_thresh_folding_width_or_height_cell == 0)
< { // interpret fold_dimension as the the folding width threshold
< // i.e. the value of transistor width above which the transistor gets folded
< w_folded_tr = fold_dimension;
< }
< else
< { // interpret fold_dimension as the height of the cell that this transistor is part of.
< double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL;
< // TODO : w_folded_tr must come from Component::compute_gate_area()
< double ratio_p_to_n = 2.0 / (2.0 + 1.0);
< if (nchannel)
< {
< w_folded_tr = (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
---
> // determine the width of the transistor after folding (if it is getting folded)
> if (next_arg_thresh_folding_width_or_height_cell == 0) {
> // interpret fold_dimension as the the folding width threshold
> // i.e. the value of transistor width above which the transistor gets folded
> w_folded_tr = fold_dimension;
> } else { // interpret fold_dimension as the height of the cell that this transistor is part of.
> double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL;
> // TODO : w_folded_tr must come from Component::compute_gate_area()
> double ratio_p_to_n = 2.0 / (2.0 + 1.0);
> if (nchannel) {
> w_folded_tr = (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
> } else {
> w_folded_tr = ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
> }
215,217c181,184
< else
< {
< w_folded_tr = ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
---
> int num_folded_tr = (int) (ceil(width / w_folded_tr));
>
> if (num_folded_tr < 2) {
> w_folded_tr = width;
219,220d185
< }
< int num_folded_tr = (int) (ceil(width / w_folded_tr));
222,225c187,193
< if (num_folded_tr < 2)
< {
< w_folded_tr = width;
< }
---
> double total_drain_w = (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + // only for drain
> (stack - 1) * g_tp.spacing_poly_to_poly;
> double drain_h_for_sidewall = w_folded_tr;
> double total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1);
> if (num_folded_tr > 1) {
> total_drain_w += (num_folded_tr - 2) * (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) +
> (num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly);
227,238c195,199
< double total_drain_w = (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + // only for drain
< (stack - 1) * g_tp.spacing_poly_to_poly;
< double drain_h_for_sidewall = w_folded_tr;
< double total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1);
< if (num_folded_tr > 1)
< {
< total_drain_w += (num_folded_tr - 2) * (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) +
< (num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly);
<
< if (num_folded_tr%2 == 0)
< {
< drain_h_for_sidewall = 0;
---
> if (num_folded_tr % 2 == 0) {
> drain_h_for_sidewall = 0;
> }
> total_drain_height_for_cap_wrt_gate *= num_folded_tr;
> drain_C_metal_connecting_folded_tr = g_tp.wire_local.C_per_um * total_drain_w;
240,242d200
< total_drain_height_for_cap_wrt_gate *= num_folded_tr;
< drain_C_metal_connecting_folded_tr = g_tp.wire_local.C_per_um * total_drain_w;
< }
244,246c202,204
< double drain_C_area = c_junc_area * total_drain_w * w_folded_tr;
< double drain_C_sidewall = c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w);
< double drain_C_wrt_gate = (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate;
---
> double drain_C_area = c_junc_area * total_drain_w * w_folded_tr;
> double drain_C_sidewall = c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w);
> double drain_C_wrt_gate = (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate;
248c206
< return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + drain_C_metal_connecting_folded_tr);
---
> return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + drain_C_metal_connecting_folded_tr);
258,260c216,217
< bool _is_wl_tr)
< {
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> const TechnologyParameter::DeviceType * dt;
262,277c219,227
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if ((!_is_dram) && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if ((!_is_dram) && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
279,280c229,230
< double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
< return (stack * restrans / width);
---
> double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
> return (stack * restrans / width);
294,296c244,245
< bool _is_wl_tr)
< {
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> const TechnologyParameter::DeviceType * dt;
298,313c247,255
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if ((!_is_dram) && (_is_cell))
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if ((!_is_dram) && (_is_cell)) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
315,316c257,258
< double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
< return (restrans / res);
---
> double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
> return (restrans / res);
322,333c264,271
< bool _is_wl_tr)
< {
< double p_to_n_sizing_ratio;
< if ((_is_dram) && (_is_wl_tr))
< { //DRAM wordline transistor
< p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio;
< }
< else
< { //DRAM or SRAM all other transistors
< p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio;
< }
< return p_to_n_sizing_ratio;
---
> bool _is_wl_tr) {
> double p_to_n_sizing_ratio;
> if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio;
> } else { //DRAM or SRAM all other transistors
> p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio;
> }
> return p_to_n_sizing_ratio;
343,349c281,285
< int rise) // whether input rises or fall
< {
< if (inputramptime == 0 && vs1 == vs2)
< {
< return tf * (vs1 < 1 ? -log(vs1) : log(vs1));
< }
< double a, b, td;
---
> int rise) { // whether input rises or fall
> if (inputramptime == 0 && vs1 == vs2) {
> return tf * (vs1 < 1 ? -log(vs1) : log(vs1));
> }
> double a, b, td;
351,362c287,297
< a = inputramptime / tf;
< if (rise == RISE)
< {
< b = 0.5;
< td = tf * sqrt(log(vs1)*log(vs1) + 2*a*b*(1.0 - vs1)) + tf*(log(vs1) - log(vs2));
< }
< else
< {
< b = 0.4;
< td = tf * sqrt(log(1.0 - vs1)*log(1.0 - vs1) + 2*a*b*(vs1)) + tf*(log(1.0 - vs1) - log(1.0 - vs2));
< }
< return (td);
---
> a = inputramptime / tf;
> if (rise == RISE) {
> b = 0.5;
> td = tf * sqrt(log(vs1) * log(vs1) + 2 * a * b * (1.0 - vs1)) +
> tf * (log(vs1) - log(vs2));
> } else {
> b = 0.4;
> td = tf * sqrt(log(1.0 - vs1) * log(1.0 - vs1) + 2 * a * b * (vs1)) +
> tf * (log(1.0 - vs1) - log(1.0 - vs2));
> }
> return (td);
370,372c305,306
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
374,386c308,315
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return nWidth*dt->I_off_n + pWidth*dt->I_off_p;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return nWidth*dt->I_off_n + pWidth*dt->I_off_p;
394,396c323,324
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
398,410c326,333
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return nwidth * dt->I_off_n;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return nwidth * dt->I_off_n;
413,418c336,340
< int factorial(int n, int m)
< {
< int fa = m, i;
< for (i=m+1; i<=n; i++)
< fa *=i;
< return fa;
---
> int factorial(int n, int m) {
> int fa = m, i;
> for (i = m + 1; i <= n; i++)
> fa *= i;
> return fa;
421,425c343,346
< int combination(int n, int m)
< {
< int ret;
< ret = factorial(n, m+1) / factorial(n - m);
< return ret;
---
> int combination(int n, int m) {
> int ret;
> ret = factorial(n, m + 1) / factorial(n - m);
> return ret;
432,434c353,354
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
436,448c356,363
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return pwidth * dt->I_off_p;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return pwidth * dt->I_off_p;
455,457c370,371
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
459,471c373,380
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return nWidth*dt->I_g_on_n;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return nWidth*dt->I_g_on_n;
478,480c387,388
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
482,494c390,397
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return pWidth*dt->I_g_on_p;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return pWidth*dt->I_g_on_p;
505,510c408,412
< enum Half_net_topology topo)
< {
< assert (fanin>=1);
< double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, _is_wl_tr);
< double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, _is_wl_tr);
< double Isub=0;
---
> enum Half_net_topology topo) {
> assert (fanin >= 1);
> double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, _is_wl_tr);
> double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, _is_wl_tr);
> double Isub = 0;
516,517c418
< switch (g_type)
< {
---
> switch (g_type) {
519,527c420,432
< if (fanin==1)
< {
< Isub = nmos_leak/num_states;
< }
< else
< {
< if (topo==parallel)
< {
< Isub=nmos_leak*fanin/num_states; //only when all tx are off, leakage power is non-zero. The possibility of this state is 1/num_states
---
> if (fanin == 1) {
> Isub = nmos_leak / num_states;
> } else {
> if (topo == parallel) {
> //only when all tx are off, leakage power is non-zero.
> //The possibility of this state is 1/num_states
> Isub = nmos_leak * fanin / num_states;
> } else {
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> //when num_off_tx ==0 there is no leakage power
> Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
529,537c434,435
< else
< {
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) //when num_off_tx ==0 there is no leakage power
< {
< //Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
< }
< Isub /=num_states;
< }
---
> Isub /= num_states;
> }
542,550c440,452
< if (fanin==1)
< {
< Isub = pmos_leak/num_states;
< }
< else
< {
< if (topo==parallel)
< {
< Isub=pmos_leak*fanin/num_states; //only when all tx are off, leakage power is non-zero. The possibility of this state is 1/num_states
---
> if (fanin == 1) {
> Isub = pmos_leak / num_states;
> } else {
> if (topo == parallel) {
> //only when all tx are off, leakage power is non-zero.
> //The possibility of this state is 1/num_states
> Isub = pmos_leak * fanin / num_states;
> } else {
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> //when num_off_tx ==0 there is no leakage power
> Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
552,560c454,455
< else
< {
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) //when num_off_tx ==0 there is no leakage power
< {
< //Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
< }
< Isub /=num_states;
< }
---
> Isub /= num_states;
> }
565c460
< Isub = (nmos_leak + pmos_leak)/2;
---
> Isub = (nmos_leak + pmos_leak) / 2;
568,572c463,468
< Isub += fanin*pmos_leak;//the pullup network
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) // the pulldown network
< {
< //Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
---
> Isub += fanin * pmos_leak;//the pullup network
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> // the pulldown network
> Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
574c470
< Isub /=num_states;
---
> Isub /= num_states;
577,580c473,477
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) // the pullup network
< {
< //Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
---
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> // the pullup network
> Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
582,583c479,480
< Isub += fanin*nmos_leak;//the pulldown network
< Isub /=num_states;
---
> Isub += fanin * nmos_leak;//the pulldown network
> Isub /= num_states;
586,588c483,486
< Isub += (nmos_leak + pmos_leak)/2;//enabled
< Isub += nmos_leak*UNI_LEAK_STACK_FACTOR; //disabled upper bound of leakage power
< Isub /=2;
---
> Isub += (nmos_leak + pmos_leak) / 2;//enabled
> //disabled upper bound of leakage power
> Isub += nmos_leak * UNI_LEAK_STACK_FACTOR;
> Isub /= 2;
591c489
< Isub = (nmos_leak + pmos_leak)/2;
---
> Isub = (nmos_leak + pmos_leak) / 2;
596c494
< }
---
> }
610,617c508,514
< enum Half_net_topology topo)
< {
< assert (fanin>=1);
< double nmos_leak = cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr);
< double pmos_leak = cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr);
< double Ig_on=0;
< int num_states;
< int num_on_tx;
---
> enum Half_net_topology topo) {
> assert (fanin >= 1);
> double nmos_leak = cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr);
> double pmos_leak = cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr);
> double Ig_on = 0;
> int num_states;
> int num_on_tx;
619c516
< num_states = int(pow(2.0, fanin));
---
> num_states = int(pow(2.0, fanin));
621,626c518,526
< switch (g_type)
< {
< case nmos:
< if (fanin==1)
< {
< Ig_on = nmos_leak/num_states;
---
> switch (g_type) {
> case nmos:
> if (fanin == 1) {
> Ig_on = nmos_leak / num_states;
> } else {
> if (topo == parallel) {
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> Ig_on += nmos_leak * combination(fanin, num_on_tx) *
> num_on_tx;
628,646c528,537
< else
< {
< if (topo==parallel)
< {
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
< }
< else
< {
< Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
< //num_on_tx is the number of on tx
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
< }
< Ig_on /=num_states;
< }
---
> } else {
> //pull down network when all TXs are on.
> Ig_on += nmos_leak * fanin;
> //num_on_tx is the number of on tx
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> //when num_on_tx=[1,n-1]
> //TODO: this is a approximation now, a precise computation
> //will be very complicated.
> Ig_on += nmos_leak * combination(fanin, num_on_tx) *
> num_on_tx / 2;
648,652c539,550
< break;
< case pmos:
< if (fanin==1)
< {
< Ig_on = pmos_leak/num_states;
---
> Ig_on /= num_states;
> }
> }
> break;
> case pmos:
> if (fanin == 1) {
> Ig_on = pmos_leak / num_states;
> } else {
> if (topo == parallel) {
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> Ig_on += pmos_leak * combination(fanin, num_on_tx) *
> num_on_tx;
654,672c552,561
< else
< {
< if (topo==parallel)
< {
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
< }
< else
< {
< Ig_on += pmos_leak * fanin;//pull down network when all TXs are on.
< //num_on_tx is the number of on tx
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
< }
< Ig_on /=num_states;
< }
---
> } else {
> //pull down network when all TXs are on.
> Ig_on += pmos_leak * fanin;
> //num_on_tx is the number of on tx
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> //when num_on_tx=[1,n-1]
> //TODO: this is a approximation now, a precise computation
> //will be very complicated.
> Ig_on += pmos_leak * combination(fanin, num_on_tx) *
> num_on_tx / 2;
674c563,566
< break;
---
> Ig_on /= num_states;
> }
> }
> break;
676,684c568,576
< case inv:
< Ig_on = (nmos_leak + pmos_leak)/2;
< break;
< case nand:
< //pull up network
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)//when num_on_tx=[1,n]
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
---
> case inv:
> Ig_on = (nmos_leak + pmos_leak) / 2;
> break;
> case nand:
> //pull up network
> //when num_on_tx=[1,n]
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx;
> }
686,700c578,593
< //pull down network
< Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
< //num_on_tx is the number of on tx
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
< }
< Ig_on /=num_states;
< break;
< case nor:
< // num_on_tx is the number of on tx in pull up network
< Ig_on += pmos_leak * fanin;//pull up network when all TXs are on.
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;
---
> //pull down network
> Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
> //num_on_tx is the number of on tx
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> //when num_on_tx=[1,n-1]
> //TODO: this is a approximation now, a precise computation will be
> //very complicated.
> Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx / 2;
> }
> Ig_on /= num_states;
> break;
> case nor:
> // num_on_tx is the number of on tx in pull up network
> Ig_on += pmos_leak * fanin;//pull up network when all TXs are on.
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx / 2;
702,721c595,615
< }
< //pull down network
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)//when num_on_tx=[1,n]
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
< Ig_on /=num_states;
< break;
< case tri:
< Ig_on += (2*nmos_leak + 2*pmos_leak)/2;//enabled
< Ig_on += (nmos_leak + pmos_leak)/2; //disabled upper bound of leakage power
< Ig_on /=2;
< break;
< case tg:
< Ig_on = (nmos_leak + pmos_leak)/2;
< break;
< default:
< assert(0);
< break;
< }
---
> }
> //pull down network
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> //when num_on_tx=[1,n]
> Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx;
> }
> Ig_on /= num_states;
> break;
> case tri:
> Ig_on += (2 * nmos_leak + 2 * pmos_leak) / 2;//enabled
> //disabled upper bound of leakage power
> Ig_on += (nmos_leak + pmos_leak) / 2;
> Ig_on /= 2;
> break;
> case tg:
> Ig_on = (nmos_leak + pmos_leak) / 2;
> break;
> default:
> assert(0);
> break;
> }
723c617
< return Ig_on;
---
> return Ig_on;
737,738c631
< double vdd)
< {
---
> double vdd) {
740,741c633,634
< double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
< double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
---
> double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
> double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
743,747c636,640
< fo_n = i_on_n/i_on_n_in;
< fo_p = i_on_p/i_on_p_in;
< fanout = c_out/c_in;
< beta_ratio = i_on_p/i_on_n;
< vt_to_vdd_ratio = vt/vdd;
---
> fo_n = i_on_n / i_on_n_in;
> fo_p = i_on_p / i_on_p_in;
> fanout = c_out / c_in;
> beta_ratio = i_on_p / i_on_n;
> vt_to_vdd_ratio = vt / vdd;
749,751c642,652
< //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
< p_short_circuit_discharge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
< p_short_circuit_charge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_n*fo_n/fanout*beta_ratio;
---
> //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
> p_short_circuit_discharge_low =
> 10 / 3 * (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) /
> pow(velocity_index, 2.0) / pow(2.0, 3 * vt_to_vdd_ratio *
> vt_to_vdd_ratio)) * c_in *
> vdd * vdd * fo_p * fo_p / fanout / beta_ratio;
> p_short_circuit_charge_low =
> 10 / 3 * (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) /
> pow(velocity_index, 2.0) / pow(2.0, 3 * vt_to_vdd_ratio *
> vt_to_vdd_ratio)) * c_in *
> vdd * vdd * fo_n * fo_n / fanout * beta_ratio;
759,760c660,665
< p_short_circuit_discharge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_p/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
< p_short_circuit_charge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_n/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
---
> p_short_circuit_discharge_high =
> pow(((vdd - vt) - vt_to_vdd_ratio), 1.5) * c_in * vdd * vdd *
> fo_p / 10 / pow(2, 3 * vt_to_vdd_ratio + 2 * velocity_index);
> p_short_circuit_charge_high = pow(((vdd - vt) - vt_to_vdd_ratio), 1.5) *
> c_in * vdd * vdd * fo_n / 10 / pow(2, 3 * vt_to_vdd_ratio + 2 *
> velocity_index);
769,771c674,676
< p_short_circuit_discharge = p_short_circuit_discharge_low;
< p_short_circuit_charge = p_short_circuit_charge_low;
< p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge)/2;
---
> p_short_circuit_discharge = p_short_circuit_discharge_low;
> p_short_circuit_charge = p_short_circuit_charge_low;
> p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge) / 2;
773c678
< return (p_short_circuit);
---
> return (p_short_circuit);
787,788c692
< double vdd)
< {
---
> double vdd) {
790,792c694,697
< double p_short_circuit=0, p_short_circuit_discharge;//, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
< double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
< double f_alpha, k_v, e, g_v_alpha, h_v_alpha;
---
> //this is actually energy
> double p_short_circuit = 0, p_short_circuit_discharge;
> double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
> double f_alpha, k_v, e, g_v_alpha, h_v_alpha;
794,803c699,716
< fo_n = i_on_n/i_on_n_in;
< fo_p = i_on_p/i_on_p_in;
< fanout = 1;
< beta_ratio = i_on_p/i_on_n;
< vt_to_vdd_ratio = vt/vdd;
< e = 2.71828;
< f_alpha = 1/(velocity_index+2) -velocity_index/(2*(velocity_index+3)) +velocity_index/(velocity_index+4)*(velocity_index/2-1);
< k_v = 0.9/0.8+(vdd-vt)/0.8*log(10*(vdd-vt)/e);
< g_v_alpha = (velocity_index + 1)*pow((1-velocity_index),velocity_index)*pow((1-velocity_index),velocity_index/2)/f_alpha/pow((1-velocity_index-velocity_index),(velocity_index/2+velocity_index+2));
< h_v_alpha = pow(2, velocity_index)*(velocity_index+1)*pow((1-velocity_index),velocity_index)/pow((1-velocity_index-velocity_index),(velocity_index+1));
---
> fo_n = i_on_n / i_on_n_in;
> fo_p = i_on_p / i_on_p_in;
> fanout = 1;
> beta_ratio = i_on_p / i_on_n;
> vt_to_vdd_ratio = vt / vdd;
> e = 2.71828;
> f_alpha = 1 / (velocity_index + 2) - velocity_index /
> (2 * (velocity_index + 3)) + velocity_index / (velocity_index + 4) *
> (velocity_index / 2 - 1);
> k_v = 0.9 / 0.8 + (vdd - vt) / 0.8 * log(10 * (vdd - vt) / e);
> g_v_alpha = (velocity_index + 1) *
> pow((1 - velocity_index), velocity_index) *
> pow((1 - velocity_index), velocity_index / 2) / f_alpha /
> pow((1 - velocity_index - velocity_index),
> (velocity_index / 2 + velocity_index + 2));
> h_v_alpha = pow(2, velocity_index) * (velocity_index + 1) *
> pow((1 - velocity_index), velocity_index) /
> pow((1 - velocity_index - velocity_index), (velocity_index + 1));
805c718
< //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
---
> //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
827,828c740,743
< p_short_circuit_discharge = k_v*vdd*vdd*c_in*fo_p*fo_p/((vdd-vt)*g_v_alpha*fanout*beta_ratio/2/k_v + h_v_alpha*fo_p);
< return (p_short_circuit);
---
> p_short_circuit_discharge = k_v * vdd * vdd * c_in * fo_p * fo_p /
> ((vdd - vt) * g_v_alpha * fanout * beta_ratio / 2 / k_v + h_v_alpha *
> fo_p);
> return (p_short_circuit);
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42,44c43,44
< uint32_t _log2(uint64_t num)
< {
< uint32_t log2 = 0;
---
> uint32_t _log2(uint64_t num) {
> uint32_t log2 = 0;
46,50c46,49
< if (num == 0)
< {
< std::cerr << "log0?" << std::endl;
< exit(1);
< }
---
> if (num == 0) {
> std::cerr << "log0?" << std::endl;
> exit(1);
> }
52,56c51,54
< while (num > 1)
< {
< num = (num >> 1);
< log2++;
< }
---
> while (num > 1) {
> num = (num >> 1);
> log2++;
> }
58c56
< return log2;
---
> return log2;
62,75c60,67
< bool is_pow2(int64_t val)
< {
< if (val <= 0)
< {
< return false;
< }
< else if (val == 1)
< {
< return true;
< }
< else
< {
< return (_log2(val) != _log2(val-1));
< }
---
> bool is_pow2(int64_t val) {
> if (val <= 0) {
> return false;
> } else if (val == 1) {
> return true;
> } else {
> return (_log2(val) != _log2(val - 1));
> }
79,81c71,72
< int powers (int base, int n)
< {
< int i, p;
---
> int powers (int base, int n) {
> int i, p;
83,86c74,77
< p = 1;
< for (i = 1; i <= n; ++i)
< p *= base;
< return p;
---
> p = 1;
> for (i = 1; i <= n; ++i)
> p *= base;
> return p;
91,94c82,84
< double logtwo (double x)
< {
< assert(x > 0);
< return ((double) (log (x) / log (2.0)));
---
> double logtwo (double x) {
> assert(x > 0);
> return ((double) (log (x) / log (2.0)));
105,107c95,96
< bool _is_wl_tr)
< {
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> const TechnologyParameter::DeviceType * dt;
109,124c98,106
< if (_is_dram && _is_cell)
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if (_is_dram && _is_wl_tr)
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if (!_is_dram && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if (_is_dram && _is_cell) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if (_is_dram && _is_wl_tr) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if (!_is_dram && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
126c108
< return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
---
> return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
137,140c119,121
< bool _is_wl_tr)
< {
< // v5.0
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> // v5.0
> const TechnologyParameter::DeviceType * dt;
142,157c123,131
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if ((!_is_dram) && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if ((!_is_dram) && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
159c133
< return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
---
> return (dt->C_g_ideal + dt->C_overlap + 3*dt->C_fringe)*width + dt->l_phy*Cpolywire;
172,175c146,148
< bool _is_wl_tr)
< {
< double w_folded_tr;
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> double w_folded_tr;
> const TechnologyParameter::DeviceType * dt;
177,192c150,158
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; // DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; // DRAM wordline transistor
< }
< else if ((!_is_dram) && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; // DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; // DRAM wordline transistor
> } else if ((!_is_dram) && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
194,198c160,164
< double c_junc_area = dt->C_junc;
< double c_junc_sidewall = dt->C_junc_sidewall;
< double c_fringe = 2*dt->C_fringe;
< double c_overlap = 2*dt->C_overlap;
< double drain_C_metal_connecting_folded_tr = 0;
---
> double c_junc_area = dt->C_junc;
> double c_junc_sidewall = dt->C_junc_sidewall;
> double c_fringe = 2 * dt->C_fringe;
> double c_overlap = 2 * dt->C_overlap;
> double drain_C_metal_connecting_folded_tr = 0;
200,213c166,179
< // determine the width of the transistor after folding (if it is getting folded)
< if (next_arg_thresh_folding_width_or_height_cell == 0)
< { // interpret fold_dimension as the the folding width threshold
< // i.e. the value of transistor width above which the transistor gets folded
< w_folded_tr = fold_dimension;
< }
< else
< { // interpret fold_dimension as the height of the cell that this transistor is part of.
< double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL;
< // TODO : w_folded_tr must come from Component::compute_gate_area()
< double ratio_p_to_n = 2.0 / (2.0 + 1.0);
< if (nchannel)
< {
< w_folded_tr = (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
---
> // determine the width of the transistor after folding (if it is getting folded)
> if (next_arg_thresh_folding_width_or_height_cell == 0) {
> // interpret fold_dimension as the the folding width threshold
> // i.e. the value of transistor width above which the transistor gets folded
> w_folded_tr = fold_dimension;
> } else { // interpret fold_dimension as the height of the cell that this transistor is part of.
> double h_tr_region = fold_dimension - 2 * g_tp.HPOWERRAIL;
> // TODO : w_folded_tr must come from Component::compute_gate_area()
> double ratio_p_to_n = 2.0 / (2.0 + 1.0);
> if (nchannel) {
> w_folded_tr = (1 - ratio_p_to_n) * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
> } else {
> w_folded_tr = ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
> }
215,217c181,184
< else
< {
< w_folded_tr = ratio_p_to_n * (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS);
---
> int num_folded_tr = (int) (ceil(width / w_folded_tr));
>
> if (num_folded_tr < 2) {
> w_folded_tr = width;
219,220d185
< }
< int num_folded_tr = (int) (ceil(width / w_folded_tr));
222,225c187,193
< if (num_folded_tr < 2)
< {
< w_folded_tr = width;
< }
---
> double total_drain_w = (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + // only for drain
> (stack - 1) * g_tp.spacing_poly_to_poly;
> double drain_h_for_sidewall = w_folded_tr;
> double total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1);
> if (num_folded_tr > 1) {
> total_drain_w += (num_folded_tr - 2) * (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) +
> (num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly);
227,238c195,199
< double total_drain_w = (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) + // only for drain
< (stack - 1) * g_tp.spacing_poly_to_poly;
< double drain_h_for_sidewall = w_folded_tr;
< double total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1);
< if (num_folded_tr > 1)
< {
< total_drain_w += (num_folded_tr - 2) * (g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact) +
< (num_folded_tr - 1) * ((stack - 1) * g_tp.spacing_poly_to_poly);
<
< if (num_folded_tr%2 == 0)
< {
< drain_h_for_sidewall = 0;
---
> if (num_folded_tr % 2 == 0) {
> drain_h_for_sidewall = 0;
> }
> total_drain_height_for_cap_wrt_gate *= num_folded_tr;
> drain_C_metal_connecting_folded_tr = g_tp.wire_local.C_per_um * total_drain_w;
240,242d200
< total_drain_height_for_cap_wrt_gate *= num_folded_tr;
< drain_C_metal_connecting_folded_tr = g_tp.wire_local.C_per_um * total_drain_w;
< }
244,246c202,204
< double drain_C_area = c_junc_area * total_drain_w * w_folded_tr;
< double drain_C_sidewall = c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w);
< double drain_C_wrt_gate = (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate;
---
> double drain_C_area = c_junc_area * total_drain_w * w_folded_tr;
> double drain_C_sidewall = c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w);
> double drain_C_wrt_gate = (c_fringe + c_overlap) * total_drain_height_for_cap_wrt_gate;
248c206
< return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + drain_C_metal_connecting_folded_tr);
---
> return (drain_C_area + drain_C_sidewall + drain_C_wrt_gate + drain_C_metal_connecting_folded_tr);
258,260c216,217
< bool _is_wl_tr)
< {
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> const TechnologyParameter::DeviceType * dt;
262,277c219,227
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if ((!_is_dram) && _is_cell)
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if ((!_is_dram) && _is_cell) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
279,280c229,230
< double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
< return (stack * restrans / width);
---
> double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
> return (stack * restrans / width);
294,296c244,245
< bool _is_wl_tr)
< {
< const TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> const TechnologyParameter::DeviceType * dt;
298,313c247,255
< if ((_is_dram) && (_is_cell))
< {
< dt = &g_tp.dram_acc; //DRAM cell access transistor
< }
< else if ((_is_dram) && (_is_wl_tr))
< {
< dt = &g_tp.dram_wl; //DRAM wordline transistor
< }
< else if ((!_is_dram) && (_is_cell))
< {
< dt = &g_tp.sram_cell; // SRAM cell access transistor
< }
< else
< {
< dt = &g_tp.peri_global;
< }
---
> if ((_is_dram) && (_is_cell)) {
> dt = &g_tp.dram_acc; //DRAM cell access transistor
> } else if ((_is_dram) && (_is_wl_tr)) {
> dt = &g_tp.dram_wl; //DRAM wordline transistor
> } else if ((!_is_dram) && (_is_cell)) {
> dt = &g_tp.sram_cell; // SRAM cell access transistor
> } else {
> dt = &g_tp.peri_global;
> }
315,316c257,258
< double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
< return (restrans / res);
---
> double restrans = (nchannel) ? dt->R_nch_on : dt->R_pch_on;
> return (restrans / res);
322,333c264,271
< bool _is_wl_tr)
< {
< double p_to_n_sizing_ratio;
< if ((_is_dram) && (_is_wl_tr))
< { //DRAM wordline transistor
< p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio;
< }
< else
< { //DRAM or SRAM all other transistors
< p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio;
< }
< return p_to_n_sizing_ratio;
---
> bool _is_wl_tr) {
> double p_to_n_sizing_ratio;
> if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> p_to_n_sizing_ratio = g_tp.dram_wl.n_to_p_eff_curr_drv_ratio;
> } else { //DRAM or SRAM all other transistors
> p_to_n_sizing_ratio = g_tp.peri_global.n_to_p_eff_curr_drv_ratio;
> }
> return p_to_n_sizing_ratio;
343,349c281,285
< int rise) // whether input rises or fall
< {
< if (inputramptime == 0 && vs1 == vs2)
< {
< return tf * (vs1 < 1 ? -log(vs1) : log(vs1));
< }
< double a, b, td;
---
> int rise) { // whether input rises or fall
> if (inputramptime == 0 && vs1 == vs2) {
> return tf * (vs1 < 1 ? -log(vs1) : log(vs1));
> }
> double a, b, td;
351,362c287,297
< a = inputramptime / tf;
< if (rise == RISE)
< {
< b = 0.5;
< td = tf * sqrt(log(vs1)*log(vs1) + 2*a*b*(1.0 - vs1)) + tf*(log(vs1) - log(vs2));
< }
< else
< {
< b = 0.4;
< td = tf * sqrt(log(1.0 - vs1)*log(1.0 - vs1) + 2*a*b*(vs1)) + tf*(log(1.0 - vs1) - log(1.0 - vs2));
< }
< return (td);
---
> a = inputramptime / tf;
> if (rise == RISE) {
> b = 0.5;
> td = tf * sqrt(log(vs1) * log(vs1) + 2 * a * b * (1.0 - vs1)) +
> tf * (log(vs1) - log(vs2));
> } else {
> b = 0.4;
> td = tf * sqrt(log(1.0 - vs1) * log(1.0 - vs1) + 2 * a * b * (vs1)) +
> tf * (log(1.0 - vs1) - log(1.0 - vs2));
> }
> return (td);
370,372c305,306
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
374,386c308,315
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return nWidth*dt->I_off_n + pWidth*dt->I_off_p;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return nWidth*dt->I_off_n + pWidth*dt->I_off_p;
394,396c323,324
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
398,410c326,333
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return nwidth * dt->I_off_n;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return nwidth * dt->I_off_n;
413,418c336,340
< int factorial(int n, int m)
< {
< int fa = m, i;
< for (i=m+1; i<=n; i++)
< fa *=i;
< return fa;
---
> int factorial(int n, int m) {
> int fa = m, i;
> for (i = m + 1; i <= n; i++)
> fa *= i;
> return fa;
421,425c343,346
< int combination(int n, int m)
< {
< int ret;
< ret = factorial(n, m+1) / factorial(n - m);
< return ret;
---
> int combination(int n, int m) {
> int ret;
> ret = factorial(n, m + 1) / factorial(n - m);
> return ret;
432,434c353,354
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
436,448c356,363
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return pwidth * dt->I_off_p;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return pwidth * dt->I_off_p;
455,457c370,371
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
459,471c373,380
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return nWidth*dt->I_g_on_n;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return nWidth*dt->I_g_on_n;
478,480c387,388
< bool _is_wl_tr)
< {
< TechnologyParameter::DeviceType * dt;
---
> bool _is_wl_tr) {
> TechnologyParameter::DeviceType * dt;
482,494c390,397
< if ((!_is_dram)&&(_is_cell))
< { //SRAM cell access transistor
< dt = &(g_tp.sram_cell);
< }
< else if ((_is_dram)&&(_is_wl_tr))
< { //DRAM wordline transistor
< dt = &(g_tp.dram_wl);
< }
< else
< { //DRAM or SRAM all other transistors
< dt = &(g_tp.peri_global);
< }
< return pWidth*dt->I_g_on_p;
---
> if ((!_is_dram) && (_is_cell)) { //SRAM cell access transistor
> dt = &(g_tp.sram_cell);
> } else if ((_is_dram) && (_is_wl_tr)) { //DRAM wordline transistor
> dt = &(g_tp.dram_wl);
> } else { //DRAM or SRAM all other transistors
> dt = &(g_tp.peri_global);
> }
> return pWidth*dt->I_g_on_p;
505,510c408,412
< enum Half_net_topology topo)
< {
< assert (fanin>=1);
< double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, _is_wl_tr);
< double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, _is_wl_tr);
< double Isub=0;
---
> enum Half_net_topology topo) {
> assert (fanin >= 1);
> double nmos_leak = simplified_nmos_leakage(nWidth, _is_dram, _is_cell, _is_wl_tr);
> double pmos_leak = simplified_pmos_leakage(pWidth, _is_dram, _is_cell, _is_wl_tr);
> double Isub = 0;
516,517c418
< switch (g_type)
< {
---
> switch (g_type) {
519,527c420,432
< if (fanin==1)
< {
< Isub = nmos_leak/num_states;
< }
< else
< {
< if (topo==parallel)
< {
< Isub=nmos_leak*fanin/num_states; //only when all tx are off, leakage power is non-zero. The possibility of this state is 1/num_states
---
> if (fanin == 1) {
> Isub = nmos_leak / num_states;
> } else {
> if (topo == parallel) {
> //only when all tx are off, leakage power is non-zero.
> //The possibility of this state is 1/num_states
> Isub = nmos_leak * fanin / num_states;
> } else {
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> //when num_off_tx ==0 there is no leakage power
> Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
529,537c434,435
< else
< {
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) //when num_off_tx ==0 there is no leakage power
< {
< //Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
< }
< Isub /=num_states;
< }
---
> Isub /= num_states;
> }
542,550c440,452
< if (fanin==1)
< {
< Isub = pmos_leak/num_states;
< }
< else
< {
< if (topo==parallel)
< {
< Isub=pmos_leak*fanin/num_states; //only when all tx are off, leakage power is non-zero. The possibility of this state is 1/num_states
---
> if (fanin == 1) {
> Isub = pmos_leak / num_states;
> } else {
> if (topo == parallel) {
> //only when all tx are off, leakage power is non-zero.
> //The possibility of this state is 1/num_states
> Isub = pmos_leak * fanin / num_states;
> } else {
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> //when num_off_tx ==0 there is no leakage power
> Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
552,560c454,455
< else
< {
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) //when num_off_tx ==0 there is no leakage power
< {
< //Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
< }
< Isub /=num_states;
< }
---
> Isub /= num_states;
> }
565c460
< Isub = (nmos_leak + pmos_leak)/2;
---
> Isub = (nmos_leak + pmos_leak) / 2;
568,572c463,468
< Isub += fanin*pmos_leak;//the pullup network
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) // the pulldown network
< {
< //Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += nmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
---
> Isub += fanin * pmos_leak;//the pullup network
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> // the pulldown network
> Isub += nmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
574c470
< Isub /=num_states;
---
> Isub /= num_states;
577,580c473,477
< for (num_off_tx=1; num_off_tx<=fanin; num_off_tx++) // the pullup network
< {
< //Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*(factorial(fanin)/(factorial(fanin, num_off_tx)*factorial(num_off_tx)));
< Isub += pmos_leak*pow(UNI_LEAK_STACK_FACTOR,(num_off_tx-1))*combination(fanin, num_off_tx);
---
> for (num_off_tx = 1; num_off_tx <= fanin; num_off_tx++) {
> // the pullup network
> Isub += pmos_leak * pow(UNI_LEAK_STACK_FACTOR,
> (num_off_tx - 1)) *
> combination(fanin, num_off_tx);
582,583c479,480
< Isub += fanin*nmos_leak;//the pulldown network
< Isub /=num_states;
---
> Isub += fanin * nmos_leak;//the pulldown network
> Isub /= num_states;
586,588c483,486
< Isub += (nmos_leak + pmos_leak)/2;//enabled
< Isub += nmos_leak*UNI_LEAK_STACK_FACTOR; //disabled upper bound of leakage power
< Isub /=2;
---
> Isub += (nmos_leak + pmos_leak) / 2;//enabled
> //disabled upper bound of leakage power
> Isub += nmos_leak * UNI_LEAK_STACK_FACTOR;
> Isub /= 2;
591c489
< Isub = (nmos_leak + pmos_leak)/2;
---
> Isub = (nmos_leak + pmos_leak) / 2;
596c494
< }
---
> }
610,617c508,514
< enum Half_net_topology topo)
< {
< assert (fanin>=1);
< double nmos_leak = cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr);
< double pmos_leak = cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr);
< double Ig_on=0;
< int num_states;
< int num_on_tx;
---
> enum Half_net_topology topo) {
> assert (fanin >= 1);
> double nmos_leak = cmos_Ig_n(nWidth, _is_dram, _is_cell, _is_wl_tr);
> double pmos_leak = cmos_Ig_p(pWidth, _is_dram, _is_cell, _is_wl_tr);
> double Ig_on = 0;
> int num_states;
> int num_on_tx;
619c516
< num_states = int(pow(2.0, fanin));
---
> num_states = int(pow(2.0, fanin));
621,626c518,526
< switch (g_type)
< {
< case nmos:
< if (fanin==1)
< {
< Ig_on = nmos_leak/num_states;
---
> switch (g_type) {
> case nmos:
> if (fanin == 1) {
> Ig_on = nmos_leak / num_states;
> } else {
> if (topo == parallel) {
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> Ig_on += nmos_leak * combination(fanin, num_on_tx) *
> num_on_tx;
628,646c528,537
< else
< {
< if (topo==parallel)
< {
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
< }
< else
< {
< Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
< //num_on_tx is the number of on tx
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
< }
< Ig_on /=num_states;
< }
---
> } else {
> //pull down network when all TXs are on.
> Ig_on += nmos_leak * fanin;
> //num_on_tx is the number of on tx
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> //when num_on_tx=[1,n-1]
> //TODO: this is a approximation now, a precise computation
> //will be very complicated.
> Ig_on += nmos_leak * combination(fanin, num_on_tx) *
> num_on_tx / 2;
648,652c539,550
< break;
< case pmos:
< if (fanin==1)
< {
< Ig_on = pmos_leak/num_states;
---
> Ig_on /= num_states;
> }
> }
> break;
> case pmos:
> if (fanin == 1) {
> Ig_on = pmos_leak / num_states;
> } else {
> if (topo == parallel) {
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> Ig_on += pmos_leak * combination(fanin, num_on_tx) *
> num_on_tx;
654,672c552,561
< else
< {
< if (topo==parallel)
< {
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
< }
< else
< {
< Ig_on += pmos_leak * fanin;//pull down network when all TXs are on.
< //num_on_tx is the number of on tx
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
< }
< Ig_on /=num_states;
< }
---
> } else {
> //pull down network when all TXs are on.
> Ig_on += pmos_leak * fanin;
> //num_on_tx is the number of on tx
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> //when num_on_tx=[1,n-1]
> //TODO: this is a approximation now, a precise computation
> //will be very complicated.
> Ig_on += pmos_leak * combination(fanin, num_on_tx) *
> num_on_tx / 2;
674c563,566
< break;
---
> Ig_on /= num_states;
> }
> }
> break;
676,684c568,576
< case inv:
< Ig_on = (nmos_leak + pmos_leak)/2;
< break;
< case nand:
< //pull up network
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)//when num_on_tx=[1,n]
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
---
> case inv:
> Ig_on = (nmos_leak + pmos_leak) / 2;
> break;
> case nand:
> //pull up network
> //when num_on_tx=[1,n]
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx;
> }
686,700c578,593
< //pull down network
< Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
< //num_on_tx is the number of on tx
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)//when num_on_tx=[1,n-1]
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;//TODO: this is a approximation now, a precise computation will be very complicated.
< }
< Ig_on /=num_states;
< break;
< case nor:
< // num_on_tx is the number of on tx in pull up network
< Ig_on += pmos_leak * fanin;//pull up network when all TXs are on.
< for (num_on_tx=1; num_on_tx<fanin; num_on_tx++)
< {
< Ig_on += pmos_leak*combination(fanin, num_on_tx)*num_on_tx/2;
---
> //pull down network
> Ig_on += nmos_leak * fanin;//pull down network when all TXs are on.
> //num_on_tx is the number of on tx
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> //when num_on_tx=[1,n-1]
> //TODO: this is a approximation now, a precise computation will be
> //very complicated.
> Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx / 2;
> }
> Ig_on /= num_states;
> break;
> case nor:
> // num_on_tx is the number of on tx in pull up network
> Ig_on += pmos_leak * fanin;//pull up network when all TXs are on.
> for (num_on_tx = 1; num_on_tx < fanin; num_on_tx++) {
> Ig_on += pmos_leak * combination(fanin, num_on_tx) * num_on_tx / 2;
702,721c595,615
< }
< //pull down network
< for (num_on_tx=1; num_on_tx<=fanin; num_on_tx++)//when num_on_tx=[1,n]
< {
< Ig_on += nmos_leak*combination(fanin, num_on_tx)*num_on_tx;
< }
< Ig_on /=num_states;
< break;
< case tri:
< Ig_on += (2*nmos_leak + 2*pmos_leak)/2;//enabled
< Ig_on += (nmos_leak + pmos_leak)/2; //disabled upper bound of leakage power
< Ig_on /=2;
< break;
< case tg:
< Ig_on = (nmos_leak + pmos_leak)/2;
< break;
< default:
< assert(0);
< break;
< }
---
> }
> //pull down network
> for (num_on_tx = 1; num_on_tx <= fanin; num_on_tx++) {
> //when num_on_tx=[1,n]
> Ig_on += nmos_leak * combination(fanin, num_on_tx) * num_on_tx;
> }
> Ig_on /= num_states;
> break;
> case tri:
> Ig_on += (2 * nmos_leak + 2 * pmos_leak) / 2;//enabled
> //disabled upper bound of leakage power
> Ig_on += (nmos_leak + pmos_leak) / 2;
> Ig_on /= 2;
> break;
> case tg:
> Ig_on = (nmos_leak + pmos_leak) / 2;
> break;
> default:
> assert(0);
> break;
> }
723c617
< return Ig_on;
---
> return Ig_on;
737,738c631
< double vdd)
< {
---
> double vdd) {
740,741c633,634
< double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
< double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
---
> double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
> double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
743,747c636,640
< fo_n = i_on_n/i_on_n_in;
< fo_p = i_on_p/i_on_p_in;
< fanout = c_out/c_in;
< beta_ratio = i_on_p/i_on_n;
< vt_to_vdd_ratio = vt/vdd;
---
> fo_n = i_on_n / i_on_n_in;
> fo_p = i_on_p / i_on_p_in;
> fanout = c_out / c_in;
> beta_ratio = i_on_p / i_on_n;
> vt_to_vdd_ratio = vt / vdd;
749,751c642,652
< //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
< p_short_circuit_discharge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
< p_short_circuit_charge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_n*fo_n/fanout*beta_ratio;
---
> //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
> p_short_circuit_discharge_low =
> 10 / 3 * (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) /
> pow(velocity_index, 2.0) / pow(2.0, 3 * vt_to_vdd_ratio *
> vt_to_vdd_ratio)) * c_in *
> vdd * vdd * fo_p * fo_p / fanout / beta_ratio;
> p_short_circuit_charge_low =
> 10 / 3 * (pow(((vdd - vt) - vt_to_vdd_ratio), 3.0) /
> pow(velocity_index, 2.0) / pow(2.0, 3 * vt_to_vdd_ratio *
> vt_to_vdd_ratio)) * c_in *
> vdd * vdd * fo_n * fo_n / fanout * beta_ratio;
759,760c660,665
< p_short_circuit_discharge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_p/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
< p_short_circuit_charge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_n/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
---
> p_short_circuit_discharge_high =
> pow(((vdd - vt) - vt_to_vdd_ratio), 1.5) * c_in * vdd * vdd *
> fo_p / 10 / pow(2, 3 * vt_to_vdd_ratio + 2 * velocity_index);
> p_short_circuit_charge_high = pow(((vdd - vt) - vt_to_vdd_ratio), 1.5) *
> c_in * vdd * vdd * fo_n / 10 / pow(2, 3 * vt_to_vdd_ratio + 2 *
> velocity_index);
769,771c674,676
< p_short_circuit_discharge = p_short_circuit_discharge_low;
< p_short_circuit_charge = p_short_circuit_charge_low;
< p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge)/2;
---
> p_short_circuit_discharge = p_short_circuit_discharge_low;
> p_short_circuit_charge = p_short_circuit_charge_low;
> p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge) / 2;
773c678
< return (p_short_circuit);
---
> return (p_short_circuit);
787,788c692
< double vdd)
< {
---
> double vdd) {
790,792c694,697
< double p_short_circuit=0, p_short_circuit_discharge;//, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
< double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
< double f_alpha, k_v, e, g_v_alpha, h_v_alpha;
---
> //this is actually energy
> double p_short_circuit = 0, p_short_circuit_discharge;
> double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
> double f_alpha, k_v, e, g_v_alpha, h_v_alpha;
794,803c699,716
< fo_n = i_on_n/i_on_n_in;
< fo_p = i_on_p/i_on_p_in;
< fanout = 1;
< beta_ratio = i_on_p/i_on_n;
< vt_to_vdd_ratio = vt/vdd;
< e = 2.71828;
< f_alpha = 1/(velocity_index+2) -velocity_index/(2*(velocity_index+3)) +velocity_index/(velocity_index+4)*(velocity_index/2-1);
< k_v = 0.9/0.8+(vdd-vt)/0.8*log(10*(vdd-vt)/e);
< g_v_alpha = (velocity_index + 1)*pow((1-velocity_index),velocity_index)*pow((1-velocity_index),velocity_index/2)/f_alpha/pow((1-velocity_index-velocity_index),(velocity_index/2+velocity_index+2));
< h_v_alpha = pow(2, velocity_index)*(velocity_index+1)*pow((1-velocity_index),velocity_index)/pow((1-velocity_index-velocity_index),(velocity_index+1));
---
> fo_n = i_on_n / i_on_n_in;
> fo_p = i_on_p / i_on_p_in;
> fanout = 1;
> beta_ratio = i_on_p / i_on_n;
> vt_to_vdd_ratio = vt / vdd;
> e = 2.71828;
> f_alpha = 1 / (velocity_index + 2) - velocity_index /
> (2 * (velocity_index + 3)) + velocity_index / (velocity_index + 4) *
> (velocity_index / 2 - 1);
> k_v = 0.9 / 0.8 + (vdd - vt) / 0.8 * log(10 * (vdd - vt) / e);
> g_v_alpha = (velocity_index + 1) *
> pow((1 - velocity_index), velocity_index) *
> pow((1 - velocity_index), velocity_index / 2) / f_alpha /
> pow((1 - velocity_index - velocity_index),
> (velocity_index / 2 + velocity_index + 2));
> h_v_alpha = pow(2, velocity_index) * (velocity_index + 1) *
> pow((1 - velocity_index), velocity_index) /
> pow((1 - velocity_index - velocity_index), (velocity_index + 1));
805c718
< //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
---
> //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
827,828c740,743
< p_short_circuit_discharge = k_v*vdd*vdd*c_in*fo_p*fo_p/((vdd-vt)*g_v_alpha*fanout*beta_ratio/2/k_v + h_v_alpha*fo_p);
< return (p_short_circuit);
---
> p_short_circuit_discharge = k_v * vdd * vdd * c_in * fo_p * fo_p /
> ((vdd - vt) * g_v_alpha * fanout * beta_ratio / 2 / k_v + h_v_alpha *
> fo_p);
> return (p_short_circuit);