1/* 2 * Copyright (c) 2012-2014, TU Delft 3 * Copyright (c) 2012-2014, TU Eindhoven 4 * Copyright (c) 2012-2014, TU Kaiserslautern 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the copyright holder nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Authors: Karthik Chandrasekar 35 * 36 */ 37 38#ifndef CMDSCHEDULER_H 39#define CMDSCHEDULER_H 40 41#include <string> 42#include <vector> 43#include <functional> // for binary_function<> 44#include <fstream> 45 46#include "MemorySpecification.h" 47#include "Utils.h" 48 49namespace Data { 50class cmdScheduler { 51 public: 52 #define READ 0 53 #define WRITE 1 54 #define ACTIVATE 2 55 #define PRECHARGE 3 56 #define POWER_DOWN 1 57 #define SELF_REFRESH 2 58 59 // the format of a transaction. 60 class trans { 61 public:
| 1/* 2 * Copyright (c) 2012-2014, TU Delft 3 * Copyright (c) 2012-2014, TU Eindhoven 4 * Copyright (c) 2012-2014, TU Kaiserslautern 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the copyright holder nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Authors: Karthik Chandrasekar 35 * 36 */ 37 38#ifndef CMDSCHEDULER_H 39#define CMDSCHEDULER_H 40 41#include <string> 42#include <vector> 43#include <functional> // for binary_function<> 44#include <fstream> 45 46#include "MemorySpecification.h" 47#include "Utils.h" 48 49namespace Data { 50class cmdScheduler { 51 public: 52 #define READ 0 53 #define WRITE 1 54 #define ACTIVATE 2 55 #define PRECHARGE 3 56 #define POWER_DOWN 1 57 #define SELF_REFRESH 2 58 59 // the format of a transaction. 60 class trans { 61 public:
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62 int type; 63 double timeStamp; 64 unsigned logicalAddress;
| 62 int64_t type; 63 int64_t timeStamp; 64 uint64_t logicalAddress;
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65 }; 66 67 std::vector<trans> transTrace; // to store the transactions. 68 69 // the format of physical address. 70 class physicalAddr { 71 public:
| 65 }; 66 67 std::vector<trans> transTrace; // to store the transactions. 68 69 // the format of physical address. 70 class physicalAddr { 71 public:
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72 unsigned rowAddr; 73 unsigned bankAddr; 74 unsigned bankGroupAddr; 75 unsigned colAddr;
| 72 uint64_t rowAddr; 73 uint64_t bankAddr; 74 uint64_t bankGroupAddr; 75 uint64_t colAddr;
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76 }; 77 78 // the format of a command. 79 class commandItem { 80 public:
| 76 }; 77 78 // the format of a command. 79 class commandItem { 80 public:
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81 int Type; 82 int bank; 83 double time;
| 81 int64_t Type; 82 int64_t bank; 83 int64_t time;
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84 std::string name; 85 physicalAddr PhysicalAddr; 86 // sorting the commands according to their scheduling time. 87 struct commandItemSorter : public std::binary_function<commandItem&, 88 commandItem&, bool>{ 89 bool operator()(const commandItem& lhs, 90 const commandItem& rhs) const 91 { 92 return lhs.time < rhs.time; 93 } 94 }; 95 }; 96 97 commandItem cmd; 98 commandItem transFinish; // the last scheduled command for a transaction. 99 commandItem PreRDWR; // the latest scheduled READ or WRITE command. 100 // the scheduled ACTIVATE commands are stored in ACT. 101 std::vector<commandItem> ACT; 102 // PRE is sued to keep recording the time when a precharge occurs. 103 std::vector<commandItem> PRE; 104 // the scheduled READ or WRITE commands are stored in RDWR. 105 std::vector<std::vector<commandItem> > RDWR; 106 // all the scheduled commands for a transaction is stored by cmdScheduling. 107 std::vector<commandItem> cmdScheduling; 108 std::vector<commandItem> cmdList; 109 unsigned elements;
| 84 std::string name; 85 physicalAddr PhysicalAddr; 86 // sorting the commands according to their scheduling time. 87 struct commandItemSorter : public std::binary_function<commandItem&, 88 commandItem&, bool>{ 89 bool operator()(const commandItem& lhs, 90 const commandItem& rhs) const 91 { 92 return lhs.time < rhs.time; 93 } 94 }; 95 }; 96 97 commandItem cmd; 98 commandItem transFinish; // the last scheduled command for a transaction. 99 commandItem PreRDWR; // the latest scheduled READ or WRITE command. 100 // the scheduled ACTIVATE commands are stored in ACT. 101 std::vector<commandItem> ACT; 102 // PRE is sued to keep recording the time when a precharge occurs. 103 std::vector<commandItem> PRE; 104 // the scheduled READ or WRITE commands are stored in RDWR. 105 std::vector<std::vector<commandItem> > RDWR; 106 // all the scheduled commands for a transaction is stored by cmdScheduling. 107 std::vector<commandItem> cmdScheduling; 108 std::vector<commandItem> cmdList; 109 unsigned elements;
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110 int BI, BC, BGI;
| 110 int64_t BI, BC, BGI;
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111 112 // the function used to translate a transaction into a sequence of 113 // commands which are scheduled to the memory.
| 111 112 // the function used to translate a transaction into a sequence of 113 // commands which are scheduled to the memory.
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114 void transTranslation(Data::MemorySpecification memSpec,
| 114 void transTranslation(const MemorySpecification& memSpec,
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115 std::ifstream& trans_trace, 116 int grouping, 117 int interleaving, 118 int burst, 119 int powerdown); 120 // get the transactions by reading the traces. 121 void getTrans(std::ifstream& pwr_trace,
| 115 std::ifstream& trans_trace, 116 int grouping, 117 int interleaving, 118 int burst, 119 int powerdown); 120 // get the transactions by reading the traces. 121 void getTrans(std::ifstream& pwr_trace,
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122 MemorySpecification memSpec);
| 122 const MemorySpecification& memSpec);
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123 // the initialization function for scheduling.
| 123 // the initialization function for scheduling.
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124 void schedulingInitialization(MemorySpecification memSpec);
| 124 void schedulingInitialization(const MemorySpecification& memSpec);
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125 // the function used to schedule commands according to the timing constraints.
| 125 // the function used to schedule commands according to the timing constraints.
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126 void analyticalScheduling(MemorySpecification memSpec);
| 126 void analyticalScheduling(const MemorySpecification& memSpec);
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127 // translate the logical address into physical address. 128 physicalAddr memoryMap(trans Trans,
| 127 // translate the logical address into physical address. 128 physicalAddr memoryMap(trans Trans,
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129 MemorySpecification memSpec);
| 129 const MemorySpecification& memSpec);
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130 // the power down and power up are scheduled by pdScheduling
| 130 // the power down and power up are scheduled by pdScheduling
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131 void pdScheduling(double endTime, 132 double timer, 133 MemorySpecification memSpec);
| 131 void pdScheduling(int64_t endTime, 132 int64_t timer, 133 const MemorySpecification& memSpec);
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134 // get the timings for scheduling a precharge since a read or write command 135 // is scheduled.
| 134 // get the timings for scheduling a precharge since a read or write command 135 // is scheduled.
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136 int getRWTP(int transType, 137 MemorySpecification memSpec);
| 136 int64_t getRWTP(int64_t transType, 137 const MemorySpecification& memSpec);
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138 // get different kind of timing constraints according to the used memory. 139 void getTimingConstraints(bool BGSwitch,
| 138 // get different kind of timing constraints according to the used memory. 139 void getTimingConstraints(bool BGSwitch,
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140 MemorySpecification memSpec, 141 int PreType, 142 int CurrentType);
| 140 const MemorySpecification& memSpec, 141 int64_t PreType, 142 int64_t CurrentType);
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143
| 143
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144 double transTime;
| 144 uint64_t uintLog2(uint64_t in); 145 146 int64_t transTime;
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145 // the flag for power down.
| 147 // the flag for power down.
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146 int power_down; 147 int Inselfrefresh; 148 int tRRD_init; 149 int tCCD_init; 150 int tWTR_init; 151 double tREF; 152 double tSwitch_init; 153 double tRWTP; 154 int bankaccess; 155 unsigned nBanks; 156 unsigned nColumns; 157 unsigned burstLength; 158 unsigned nbrOfBankGroups;
| 148 int64_t power_down; 149 int64_t Inselfrefresh; 150 int64_t tRRD_init; 151 int64_t tCCD_init; 152 int64_t tWTR_init; 153 int64_t tREF; 154 int64_t tSwitch_init; 155 int64_t tRWTP; 156 int64_t bankaccess; 157 int64_t nBanks; 158 int64_t nColumns; 159 int64_t burstLength; 160 int64_t nbrOfBankGroups;
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159 bool timingsGet;
| 161 bool timingsGet;
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160 double startTime;
| 162 int64_t startTime;
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161 162 // the scheduling results for all the transactions are written into 163 // commands which will be used by the power analysis part. 164 std::ofstream commands; 165}; 166} 167 168#endif // ifndef CMDSCHEDULER_H
| 163 164 // the scheduling results for all the transactions are written into 165 // commands which will be used by the power analysis part. 166 std::ofstream commands; 167}; 168} 169 170#endif // ifndef CMDSCHEDULER_H
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