| README.md (11555:2efa95cf8504) | README.md (12266:63b8da9eeca4) |
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| 1# DRAM Power Model (DRAMPower) 2[](https://travis-ci.org/ravenrd/DRAMPower) 3[](https://coveralls.io/r/ravenrd/DRAMPower?branch=master) 4## 0. Releases 5 6The last official release can be found here: 7https://github.com/ravenrd/DRAMPower/releases/tag/4.0 8 9The master branch of the repository should be regarded as the bleeding-edge version, which has all the latest features, but also all the latest bugs. Use at your own discretion. 10 11## 1. Installation 12 | 1# DRAM Power Model (DRAMPower) 2[](https://travis-ci.org/ravenrd/DRAMPower) 3[](https://coveralls.io/r/ravenrd/DRAMPower?branch=master) 4## 0. Releases 5 6The last official release can be found here: 7https://github.com/ravenrd/DRAMPower/releases/tag/4.0 8 9The master branch of the repository should be regarded as the bleeding-edge version, which has all the latest features, but also all the latest bugs. Use at your own discretion. 10 11## 1. Installation 12 |
| 13Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. src/cli/drampower.cc file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: | 13Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. [drampower.cc](src/cli/drampower.cc) file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: |
| 14```bash 15make -j4 16``` 17This command will download a set of trace files from https://github.com/Sv3n/DRAMPowerTraces which can be used as test input for the tool. 18 19## 2. Required Packages 20 21The tool was verified on Ubuntu 14.04 using: --- 9 unchanged lines hidden (view full) --- 31 32## 4. Trace Specification 33### Command Traces 34If the command-level interface is being used, a command trace can be logged in a file. 35An example is given in ```traces/commands.trace``` 36 37The format it uses is: ```<timestamp>,<command>,<bank>```. 38For example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is | 14```bash 15make -j4 16``` 17This command will download a set of trace files from https://github.com/Sv3n/DRAMPowerTraces which can be used as test input for the tool. 18 19## 2. Required Packages 20 21The tool was verified on Ubuntu 14.04 using: --- 9 unchanged lines hidden (view full) --- 31 32## 4. Trace Specification 33### Command Traces 34If the command-level interface is being used, a command trace can be logged in a file. 35An example is given in ```traces/commands.trace``` 36 37The format it uses is: ```<timestamp>,<command>,<bank>```. 38For example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is |
| 39mentioned in src/MemCommand.h and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be | 39mentioned in [MemCommand.h](src/MemCommand.h) and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be |
| 40specified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder. 41 42### Transaction Traces 43If the transaction-level interface is being used, a transaction trace can be logged. 44 45The format it uses is: ```<timestamp>,<transaction_type>,<address>```. 46For example, "35,READ,0x80028", where READ/WRITE can be the transaction type and the logical address (32-bits long and byte addressable) less than the maximum supported DRAM capacity of 4GB (32Gb). 47 48The tool uses a flexible and efficient memory map as follows: specified in HEX (0x). Timestamp is in clock cycles (cc) and maximum {row}-{bank}-{column}-{BI}-{BC}-{BGI}-{BL} 49Here, BI gives the degree of bank interleaving, BC gives the burst size (count), BGI gives the degree of bank group interleaving (for DDR4) and BL gives the burst length used by the device. 50Dual-Rank addressing is not yet supported. The BC and BL address bits are derived from the column address bits, whereas the BI and BGI bits are derived from the bank address bits. 51 52Four sample MediaBench application transaction traces have been provided. The MediaBench applications include: (1) EPIC Encoder, (2) JPEG Encoder, (3) H263 Encoder and (4) MPEG2 Encoder. These applications were independently executed on the SimpleScalar simulator with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and logged them as transaction traces. These can be used with our command scheduler to generate equivalent command traces for any DRAM memory specified. 53 54## 5. Usage 55 | 40specified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder. 41 42### Transaction Traces 43If the transaction-level interface is being used, a transaction trace can be logged. 44 45The format it uses is: ```<timestamp>,<transaction_type>,<address>```. 46For example, "35,READ,0x80028", where READ/WRITE can be the transaction type and the logical address (32-bits long and byte addressable) less than the maximum supported DRAM capacity of 4GB (32Gb). 47 48The tool uses a flexible and efficient memory map as follows: specified in HEX (0x). Timestamp is in clock cycles (cc) and maximum {row}-{bank}-{column}-{BI}-{BC}-{BGI}-{BL} 49Here, BI gives the degree of bank interleaving, BC gives the burst size (count), BGI gives the degree of bank group interleaving (for DDR4) and BL gives the burst length used by the device. 50Dual-Rank addressing is not yet supported. The BC and BL address bits are derived from the column address bits, whereas the BI and BGI bits are derived from the bank address bits. 51 52Four sample MediaBench application transaction traces have been provided. The MediaBench applications include: (1) EPIC Encoder, (2) JPEG Encoder, (3) H263 Encoder and (4) MPEG2 Encoder. These applications were independently executed on the SimpleScalar simulator with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and logged them as transaction traces. These can be used with our command scheduler to generate equivalent command traces for any DRAM memory specified. 53 54## 5. Usage 55 |
| 56src/cli/drampower.cc is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. | 56[drampower.cc](src/cli/drampower.cc) is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. |
| 57 58To use DRAMPower at the command-level (command trace), after make, use the following: 59```bash 60./drampower -m <memory spec (ID)> -c <commands trace> 61``` 62To use DRAMPower at the transaction-level (command scheduler), after make, use the 63following: 64```bash --- 38 unchanged lines hidden (view full) --- 103or (3) include +3 sigma variation (3s). These measures are derived based on the 104Monte-Carlo analysis performed on our SPICE-based DRAM cross-section. 105 106To include these XMLs in your simulations, simply use them as the target memory. 107 108## 8. Example Usage 109 110An example of using this tool is provided below. To compile the example, | 57 58To use DRAMPower at the command-level (command trace), after make, use the following: 59```bash 60./drampower -m <memory spec (ID)> -c <commands trace> 61``` 62To use DRAMPower at the transaction-level (command scheduler), after make, use the 63following: 64```bash --- 38 unchanged lines hidden (view full) --- 103or (3) include +3 sigma variation (3s). These measures are derived based on the 104Monte-Carlo analysis performed on our SPICE-based DRAM cross-section. 105 106To include these XMLs in your simulations, simply use them as the target memory. 107 108## 8. Example Usage 109 110An example of using this tool is provided below. To compile the example, |
| 111use the Makefile and make sure the Gcc and Xerces-c are installed. Then, run: | 111use the Makefile and make sure the gcc and Xerces-c are installed. Then, run: |
| 112``` 113make -j4 114``` | 112``` 113make -j4 114``` |
| 115 116This should show the following compilation message on the screen: 117``` 118g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/xmlparser/MemSpecParser.d -iquote src -o src/xmlparser/MemSpecParser.o -c src/xmlparser/MemSpecParser.cc 119g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/xmlparser/XMLHandler.d -iquote src -o src/xmlparser/XMLHandler.o -c src/xmlparser/XMLHandler.cc 120g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/xmlparser/XMLParser.d -iquote src -o src/xmlparser/XMLParser.o -c src/xmlparser/XMLParser.cc 121g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/CmdScheduler.d -iquote src -o src/CmdScheduler.o -c src/CmdScheduler.cc 122g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/CommandAnalysis.d -iquote src -o src/CommandAnalysis.o -c src/CommandAnalysis.cc 123g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/MemArchitectureSpec.d -iquote src -o src/MemArchitectureSpec.o -c src/MemArchitectureSpec.cc 124g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/MemCommand.d -iquote src -o src/MemCommand.o -c src/MemCommand.cc 125g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/MemoryPowerModel.d -iquote src -o src/MemoryPowerModel.o -c src/MemoryPowerModel.cc 126g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/MemorySpecification.d -iquote src -o src/MemorySpecification.o -c src/MemorySpecification.cc 127g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/MemPowerSpec.d -iquote src -o src/MemPowerSpec.o -c src/MemPowerSpec.cc 128g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/MemTimingSpec.d -iquote src -o src/MemTimingSpec.o -c src/MemTimingSpec.cc 129g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/Parameter.d -iquote src -o src/Parameter.o -c src/Parameter.cc 130g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/Parametrisable.d -iquote src -o src/Parametrisable.o -c src/Parametrisable.cc 131g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/TraceParser.d -iquote src -o src/TraceParser.o -c src/TraceParser.cc 132g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral -Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF src/libdrampower/LibDRAMPower.d -iquote src -o src/libdrampower/LibDRAMPower.o -c src/libdrampower/LibDRAMPower.cc 133ar -cvr src/libdrampowerxml.a src/xmlparser/MemSpecParser.o src/xmlparser/XMLHandler.o src/xmlparser/XMLParser.o 134a - src/xmlparser/MemSpecParser.o 135a - src/xmlparser/XMLHandler.o 136a - src/xmlparser/XMLParser.o 137g++ -Wall -o drampower src/xmlparser/MemSpecParser.o src/xmlparser/XMLHandler.o src/xmlparser/XMLParser.o src/CmdScheduler.o src/CommandAnalysis.o src/MemArchitectureSpec.o src/MemCommand.o src/MemoryPowerModel.o src/MemorySpecification.o src/MemPowerSpec.o src/MemTimingSpec.o src/Parameter.o src/Parametrisable.o src/TraceParser.o -L/usr/lib -lxerces-c 138ar -cvr src/libdrampower.a src/CmdScheduler.o src/CommandAnalysis.o src/MemArchitectureSpec.o src/MemCommand.o src/MemoryPowerModel.o src/MemorySpecification.o src/MemPowerSpec.o src/MemTimingSpec.o src/Parameter.o src/Parametrisable.o src/TraceParser.o src/libdrampower/LibDRAMPower.o 139a - src/CmdScheduler.o 140a - src/CommandAnalysis.o 141a - src/MemArchitectureSpec.o 142a - src/MemCommand.o 143a - src/MemoryPowerModel.o 144a - src/MemorySpecification.o 145a - src/MemPowerSpec.o 146a - src/MemTimingSpec.o 147a - src/Parameter.o 148a - src/Parametrisable.o 149a - src/TraceParser.o 150a - src/libdrampower/LibDRAMPower.o 151``` | |
| 152After this, run with the command trace or the transaction trace, as described before: 153``` 154./drampower -m memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml -t traces/mediabench-epic.trace -r 155``` 156The output should be something like this: 157 158``` 159* Parsing memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml | 115After this, run with the command trace or the transaction trace, as described before: 116``` 117./drampower -m memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml -t traces/mediabench-epic.trace -r 118``` 119The output should be something like this: 120 121``` 122* Parsing memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml |
| 160* Analysis start time: Thu Nov 14 01:44:24 2013 | 123* Analysis start time: Thu Aug 4 15:43:52 2016 |
| 161* Analyzing the input trace | 124* Analyzing the input trace |
| 162* Analysis End Time: Thu Nov 14 01:44:26 2013 163* Power Computation Start time: Thu Nov 14 01:44:26 2013 | |
| 164* Trace Details: | 125* Trace Details: |
| 165Number of Activates: 96984 166Number of Reads: 67179 167Number of Writes: 29805 168Number of Precharges: 96984 169Number of Refreshes: 13168 170Number of Active Cycles: 2519793 171 Number of Active Idle Cycles: 196851 172 Number of Active Power-Up Cycles: 0 173 Number of Auto-Refresh Active cycles during Self-Refresh Power-Up: 0 174Number of Precharged Cycles: 52261474 175 Number of Precharged Idle Cycles: 51649664 176 Number of Precharged Power-Up Cycles: 0 177 Number of Auto-Refresh Precharged cycles during Self-Refresh Power-Up: 0 178 Number of Self-Refresh Power-Up Cycles: 0 179Total Idle Cycles (Active + Precharged): 51846515 180Number of Power-Downs: 0 181 Number of Active Fast-exit Power-Downs: 0 182 Number of Active Slow-exit Power-Downs: 0 183 Number of Precharged Fast-exit Power-Downs: 0 184 Number of Precharged Slow-exit Power-Downs: 0 185Number of Power-Down Cycles: 0 186 Number of Active Fast-exit Power-Down Cycles: 0 187 Number of Active Slow-exit Power-Down Cycles: 0 188 Number of Auto-Refresh Active cycles during Self-Refresh: 0 189 Number of Precharged Fast-exit Power-Down Cycles: 0 190 Number of Precharged Slow-exit Power-Down Cycles: 0 191 Number of Auto-Refresh Precharged cycles during Self-Refresh: 0 192Number of Auto-Refresh Cycles: 776912 193Number of Self-Refreshes: 0 194Number of Self-Refresh Cycles: 0 | 126 127#ACT commands: 96984 128#RD + #RDA commands: 67179 129#WR + #WRA commands: 29805 130#PRE (+ PREA) commands: 96984 131#REF commands: 13168 132#Active Cycles: 2519793 133 #Active Idle Cycles: 196851 134 #Active Power-Up Cycles: 0 135 #Auto-Refresh Active cycles during Self-Refresh Power-Up: 0 136#Precharged Cycles: 52261474 137 #Precharged Idle Cycles: 51649629 138 #Precharged Power-Up Cycles: 0 139 #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: 0 140 #Self-Refresh Power-Up Cycles: 0 141Total Idle Cycles (Active + Precharged): 51846480 142#Power-Downs: 0 143 #Active Fast-exit Power-Downs: 0 144 #Active Slow-exit Power-Downs: 0 145 #Precharged Fast-exit Power-Downs: 0 146 #Precharged Slow-exit Power-Downs: 0 147#Power-Down Cycles: 0 148 #Active Fast-exit Power-Down Cycles: 0 149 #Active Slow-exit Power-Down Cycles: 0 150 #Auto-Refresh Active cycles during Self-Refresh: 0 151 #Precharged Fast-exit Power-Down Cycles: 0 152 #Precharged Slow-exit Power-Down Cycles: 0 153 #Auto-Refresh Precharged cycles during Self-Refresh: 0 154#Auto-Refresh Cycles: 776912 155#Self-Refreshes: 0 156#Self-Refresh Cycles: 0 |
| 195---------------------------------------- 196Total Trace Length (clock cycles): 54781267 197---------------------------------------- 198 199* Trace Power and Energy Estimates: | 157---------------------------------------- 158Total Trace Length (clock cycles): 54781267 159---------------------------------------- 160 161* Trace Power and Energy Estimates: |
| 162 |
|
| 200ACT Cmd Energy: 109175234.52 pJ 201PRE Cmd Energy: 47764165.10 pJ 202RD Cmd Energy: 49155365.85 pJ | 163ACT Cmd Energy: 109175234.52 pJ 164PRE Cmd Energy: 47764165.10 pJ 165RD Cmd Energy: 49155365.85 pJ |
| 203WR Cmd Energy: 23486116.32 pJ 204RD I/O Energy: 22249684.80 pJ 205WR Termination Energy: 50549280.00 pJ | 166WR Cmd Energy: 23486116.32 pJRD I/O Energy: 20872124.58 pJ 167WR Termination Energy: 47419587.24 pJ |
| 206ACT Stdby Energy: 283653996.25 pJ 207 Active Idle Energy: 22159587.24 pJ 208 Active Power-Up Energy: 0.00 pJ 209 Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ 210PRE Stdby Energy: 5147706163.23 pJ | 168ACT Stdby Energy: 283653996.25 pJ 169 Active Idle Energy: 22159587.24 pJ 170 Active Power-Up Energy: 0.00 pJ 171 Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ 172PRE Stdby Energy: 5147706163.23 pJ |
| 211 Precharge Idle Energy: 5087443452.16 pJ | 173 Precharge Idle Energy: 5087440004.69 pJ |
| 212 Precharged Power-Up Energy: 0.00 pJ 213 Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ 214 Self-Refresh Power-Up Energy: 0.00 pJ | 174 Precharged Power-Up Energy: 0.00 pJ 175 Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ 176 Self-Refresh Power-Up Energy: 0.00 pJ |
| 215Total Idle Energy (Active + Precharged): 5109603039.40 pJ | 177Total Idle Energy (Active + Precharged): 5109599591.93 pJ |
| 216Total Power-Down Energy: 0.00 pJ 217 Fast-Exit Active Power-Down Energy: 0.00 pJ 218 Slow-Exit Active Power-Down Energy: 0.00 pJ 219 Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ 220 Fast-Exit Precharged Power-Down Energy: 0.00 pJ 221 Slow-Exit Precharged Power-Down Energy: 0.00 pJ 222 Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ 223Auto-Refresh Energy: 262371782.36 pJ 224Self-Refresh Energy: 0.00 pJ 225---------------------------------------- | 178Total Power-Down Energy: 0.00 pJ 179 Fast-Exit Active Power-Down Energy: 0.00 pJ 180 Slow-Exit Active Power-Down Energy: 0.00 pJ 181 Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ 182 Fast-Exit Precharged Power-Down Energy: 0.00 pJ 183 Slow-Exit Precharged Power-Down Energy: 0.00 pJ 184 Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ 185Auto-Refresh Energy: 262371782.36 pJ 186Self-Refresh Energy: 0.00 pJ 187---------------------------------------- |
| 226Total Trace Energy: 5996111788.44 pJ 227Average Power: 58.34 mW | 188Total Trace Energy: 5991604535.46 pJ 189Average Power: 58.30 mW |
| 228---------------------------------------- | 190---------------------------------------- |
| 229* Power Computation End time: Thu Nov 14 01:44:27 2013 230* Total Simulation time: 3.51 seconds | 191* Power Computation End time: Thu Aug 4 15:43:59 2016 192* Total Simulation time: 7 seconds |
| 231* 232``` 233 234As can be noticed, the tool performs DRAM command scheduling and reports the number 235of activates, precharges, reads, writes, refreshes, power-downs and self-refreshes 236besides the number of clock cycles spent in the active and precharged states, in the 237power-down (fast/slow-exit) and self-refresh states and in the idle mode. It also 238reports the energy consumption of these components, besides the IO and Termination 239components in pJ (pico Joules) and the average power consumption of the trace in mW. 240It also reports the simulation start/end times and the total simulation time in seconds. 241 242## 9. DRAMPower Library 243 244The DRAMPower tool has an additional feature and can be used as a library. | 193* 194``` 195 196As can be noticed, the tool performs DRAM command scheduling and reports the number 197of activates, precharges, reads, writes, refreshes, power-downs and self-refreshes 198besides the number of clock cycles spent in the active and precharged states, in the 199power-down (fast/slow-exit) and self-refresh states and in the idle mode. It also 200reports the energy consumption of these components, besides the IO and Termination 201components in pJ (pico Joules) and the average power consumption of the trace in mW. 202It also reports the simulation start/end times and the total simulation time in seconds. 203 204## 9. DRAMPower Library 205 206The DRAMPower tool has an additional feature and can be used as a library. |
| 245In order to use the library run "make lib", include src/libdrampower/LibDRAMPower.h in your project and | 207In order to use the library run "make lib", include [LibDRAMPower.h](src/libdrampower/LibDRAMPower.h) in your project and |
| 246link the file src/libdrampower.a with your project. | 208link the file src/libdrampower.a with your project. |
| 247An example for the usuage of the library can be found in the folder test/libdrampowertest/lib_test.cc | 209Examples for the usage of the library are [lib_test.cc](test/libdrampowertest/lib_test.cc) and [window_example.cc](test/libdrampowertest/window_example.cc). |
| 248 249## 10. Authors & Acknowledgment 250 | 210 211## 10. Authors & Acknowledgment 212 |
| 251The tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven and verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations. This tool has been developed by Karthik Chandrasekar with Yonghui Li under the supervision of Dr. Benny Akesson and Prof. Kees Goossens. The IO and Termination Power measures have been employed from Micron's DRAM Power Calculator. If you decide to use DRAMPower in your research, please cite one of the following references: | 213The tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven 214and verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations. This tool has been developed by 215Karthik Chandrasekar with Yonghui Li under the supervision of Dr. Benny Akesson and Prof. Kees Goossens. The IO and Termination Power measures have been employed 216from Micron's DRAM Power Calculator. If you decide to use DRAMPower in your research, please cite one of the following references: |
| 252 253**To cite the DRAMPower Tool:** 254``` 255[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool 256Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens 257URL: http://www.drampower.info 258``` 259 --- 39 unchanged lines hidden --- | 217 218**To cite the DRAMPower Tool:** 219``` 220[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool 221Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens 222URL: http://www.drampower.info 223``` 224 --- 39 unchanged lines hidden --- |