1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# 2016 Georgia Institute of Technology
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29# Tushar Krishna
30
31from m5.params import *
32from m5.objects import *
33
34from BaseTopology import SimpleTopology
35
36# Creates a generic Mesh assuming an equal number of cache
37# and directory controllers.
38# XY routing is enforced (using link weights)
39# to guarantee deadlock freedom.
40
41class Mesh_XY(SimpleTopology):
42 description='Mesh_XY'
43
44 def __init__(self, controllers):
45 self.nodes = controllers
46
47 # Makes a generic mesh
48 # assuming an equal number of cache and directory cntrls
49
50 def makeTopology(self, options, network, IntLink, ExtLink, Router):
51 nodes = self.nodes
52
53 num_routers = options.num_cpus
54 num_rows = options.mesh_rows
55
56 # There must be an evenly divisible number of cntrls to routers
57 # Also, obviously the number or rows must be <= the number of routers
58 cntrls_per_router, remainder = divmod(len(nodes), num_routers)
59 assert(num_rows <= num_routers)
60 num_columns = int(num_routers / num_rows)
61 assert(num_columns * num_rows == num_routers)
62
63 # Create the routers in the mesh
64 routers = [Router(router_id=i) for i in range(num_routers)]
65 network.routers = routers
66
67 # link counter to set unique link ids
68 link_count = 0
69
70 # Add all but the remainder nodes to the list of nodes to be uniformly
71 # distributed across the network.
72 network_nodes = []
73 remainder_nodes = []
74 for node_index in xrange(len(nodes)):
75 if node_index < (len(nodes) - remainder):
76 network_nodes.append(nodes[node_index])
77 else:
78 remainder_nodes.append(nodes[node_index])
79
80 # Connect each node to the appropriate router
81 ext_links = []
82 for (i, n) in enumerate(network_nodes):
83 cntrl_level, router_id = divmod(i, num_routers)
84 assert(cntrl_level < cntrls_per_router)
85 ext_links.append(ExtLink(link_id=link_count, ext_node=n,
86 int_node=routers[router_id]))
87 link_count += 1
88
89 # Connect the remainding nodes to router 0. These should only be
90 # DMA nodes.
91 for (i, node) in enumerate(remainder_nodes):
92 assert(node.type == 'DMA_Controller')
93 assert(i < remainder)
94 ext_links.append(ExtLink(link_id=link_count, ext_node=node,
95 int_node=routers[0]))
96 link_count += 1
97
98 network.ext_links = ext_links
99
100 # Create the mesh links.
101 int_links = []
102
103 # East output to West input links (weight = 1)
104 for row in xrange(num_rows):
105 for col in xrange(num_columns):
106 if (col + 1 < num_columns):
107 east_out = col + (row * num_columns)
108 west_in = (col + 1) + (row * num_columns)
109 int_links.append(IntLink(link_id=link_count,
110 src_node=routers[east_out],
111 dst_node=routers[west_in],
| 1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# 2016 Georgia Institute of Technology
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29# Tushar Krishna
30
31from m5.params import *
32from m5.objects import *
33
34from BaseTopology import SimpleTopology
35
36# Creates a generic Mesh assuming an equal number of cache
37# and directory controllers.
38# XY routing is enforced (using link weights)
39# to guarantee deadlock freedom.
40
41class Mesh_XY(SimpleTopology):
42 description='Mesh_XY'
43
44 def __init__(self, controllers):
45 self.nodes = controllers
46
47 # Makes a generic mesh
48 # assuming an equal number of cache and directory cntrls
49
50 def makeTopology(self, options, network, IntLink, ExtLink, Router):
51 nodes = self.nodes
52
53 num_routers = options.num_cpus
54 num_rows = options.mesh_rows
55
56 # There must be an evenly divisible number of cntrls to routers
57 # Also, obviously the number or rows must be <= the number of routers
58 cntrls_per_router, remainder = divmod(len(nodes), num_routers)
59 assert(num_rows <= num_routers)
60 num_columns = int(num_routers / num_rows)
61 assert(num_columns * num_rows == num_routers)
62
63 # Create the routers in the mesh
64 routers = [Router(router_id=i) for i in range(num_routers)]
65 network.routers = routers
66
67 # link counter to set unique link ids
68 link_count = 0
69
70 # Add all but the remainder nodes to the list of nodes to be uniformly
71 # distributed across the network.
72 network_nodes = []
73 remainder_nodes = []
74 for node_index in xrange(len(nodes)):
75 if node_index < (len(nodes) - remainder):
76 network_nodes.append(nodes[node_index])
77 else:
78 remainder_nodes.append(nodes[node_index])
79
80 # Connect each node to the appropriate router
81 ext_links = []
82 for (i, n) in enumerate(network_nodes):
83 cntrl_level, router_id = divmod(i, num_routers)
84 assert(cntrl_level < cntrls_per_router)
85 ext_links.append(ExtLink(link_id=link_count, ext_node=n,
86 int_node=routers[router_id]))
87 link_count += 1
88
89 # Connect the remainding nodes to router 0. These should only be
90 # DMA nodes.
91 for (i, node) in enumerate(remainder_nodes):
92 assert(node.type == 'DMA_Controller')
93 assert(i < remainder)
94 ext_links.append(ExtLink(link_id=link_count, ext_node=node,
95 int_node=routers[0]))
96 link_count += 1
97
98 network.ext_links = ext_links
99
100 # Create the mesh links.
101 int_links = []
102
103 # East output to West input links (weight = 1)
104 for row in xrange(num_rows):
105 for col in xrange(num_columns):
106 if (col + 1 < num_columns):
107 east_out = col + (row * num_columns)
108 west_in = (col + 1) + (row * num_columns)
109 int_links.append(IntLink(link_id=link_count,
110 src_node=routers[east_out],
111 dst_node=routers[west_in],
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