Mesh_XY.py (13774:a1be2a0c55f2) | Mesh_XY.py (13885:d10ea5e56cb0) |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# 2016 Georgia Institute of Technology 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29# Tushar Krishna 30 31from __future__ import print_function 32from __future__ import absolute_import 33 34from m5.params import * 35from m5.objects import * 36 | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# 2016 Georgia Institute of Technology 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29# Tushar Krishna 30 31from __future__ import print_function 32from __future__ import absolute_import 33 34from m5.params import * 35from m5.objects import * 36 |
37from common import FileSystemConfig 38 |
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37from .BaseTopology import SimpleTopology 38 39# Creates a generic Mesh assuming an equal number of cache 40# and directory controllers. 41# XY routing is enforced (using link weights) 42# to guarantee deadlock freedom. 43 44class Mesh_XY(SimpleTopology): --- 124 unchanged lines hidden (view full) --- 169 src_outport="South", 170 dst_inport="North", 171 latency = link_latency, 172 weight=2)) 173 link_count += 1 174 175 176 network.int_links = int_links | 39from .BaseTopology import SimpleTopology 40 41# Creates a generic Mesh assuming an equal number of cache 42# and directory controllers. 43# XY routing is enforced (using link weights) 44# to guarantee deadlock freedom. 45 46class Mesh_XY(SimpleTopology): --- 124 unchanged lines hidden (view full) --- 171 src_outport="South", 172 dst_inport="North", 173 latency = link_latency, 174 weight=2)) 175 link_count += 1 176 177 178 network.int_links = int_links |
179 180 # Register nodes with filesystem 181 def registerTopology(self, options): 182 for i in xrange(options.num_cpus): 183 FileSystemConfig.register_node([i], 184 MemorySize(options.mem_size) / options.num_cpus, i) |
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