1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
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5# modification, are permitted provided that the following conditions are
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Brad Beckmann
28
29from __future__ import print_function
30from __future__ import absolute_import
31
32from m5.params import *
33from m5.objects import *
34
35from common import FileSystemConfig
36
37from .BaseTopology import SimpleTopology
38
39# Creates a Mesh topology with 4 directories, one at each corner.
40# One L1 (and L2, depending on the protocol) are connected to each router.
41# XY routing is enforced (using link weights) to guarantee deadlock freedom.
42
43class MeshDirCorners_XY(SimpleTopology):
44 description='MeshDirCorners_XY'
45
46 def __init__(self, controllers):
47 self.nodes = controllers
48
49 def makeTopology(self, options, network, IntLink, ExtLink, Router):
50 nodes = self.nodes
51
52 num_routers = options.num_cpus
53 num_rows = options.mesh_rows
54
55 # default values for link latency and router latency.
56 # Can be over-ridden on a per link/router basis
57 link_latency = options.link_latency # used by simple and garnet
58 router_latency = options.router_latency # only used by garnet
59
60
61 # First determine which nodes are cache cntrls vs. dirs vs. dma
62 cache_nodes = []
63 dir_nodes = []
64 dma_nodes = []
65 for node in nodes:
66 if node.type == 'L1Cache_Controller' or \
67 node.type == 'L2Cache_Controller':
68 cache_nodes.append(node)
69 elif node.type == 'Directory_Controller':
70 dir_nodes.append(node)
71 elif node.type == 'DMA_Controller':
72 dma_nodes.append(node)
73
74 # Obviously the number or rows must be <= the number of routers
75 # and evenly divisible. Also the number of caches must be a
76 # multiple of the number of routers and the number of directories
77 # must be four.
78 assert(num_rows > 0 and num_rows <= num_routers)
79 num_columns = int(num_routers / num_rows)
80 assert(num_columns * num_rows == num_routers)
81 caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
82 assert(remainder == 0)
83 assert(len(dir_nodes) == 4)
84
85 # Create the routers in the mesh
86 routers = [Router(router_id=i, latency = router_latency) \
87 for i in range(num_routers)]
88 network.routers = routers
89
90 # link counter to set unique link ids
91 link_count = 0
92
93 # Connect each cache controller to the appropriate router
94 ext_links = []
95 for (i, n) in enumerate(cache_nodes):
96 cntrl_level, router_id = divmod(i, num_routers)
97 assert(cntrl_level < caches_per_router)
98 ext_links.append(ExtLink(link_id=link_count, ext_node=n,
99 int_node=routers[router_id],
100 latency = link_latency))
101 link_count += 1
102
103 # NUMA Node for each quadrant
104 # With odd columns or rows, the nodes will be unequal
105 numa_nodes = [ [], [], [], []]
106 for i in xrange(num_routers):
107 if i % num_columns < num_columns / 2 and \
108 i < num_routers / 2:
109 numa_nodes[0].append(i)
110 elif i % num_columns >= num_columns / 2 and \
111 i < num_routers / 2:
112 numa_nodes[1].append(i)
113 elif i % num_columns < num_columns / 2 and \
114 i >= num_routers / 2:
115 numa_nodes[2].append(i)
116 else:
117 numa_nodes[3].append(i)
118
119 num_numa_nodes = 0
120 for n in numa_nodes:
121 if n:
122 num_numa_nodes += 1
123
124 # Connect the dir nodes to the corners.
125 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
126 int_node=routers[0],
127 latency = link_latency))
128 link_count += 1
129 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1],
130 int_node=routers[num_columns - 1],
131 latency = link_latency))
132 link_count += 1
133 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2],
134 int_node=routers[num_routers - num_columns],
135 latency = link_latency))
136 link_count += 1
137 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3],
138 int_node=routers[num_routers - 1],
139 latency = link_latency))
140 link_count += 1
141
142 # Connect the dma nodes to router 0. These should only be DMA nodes.
143 for (i, node) in enumerate(dma_nodes):
144 assert(node.type == 'DMA_Controller')
145 ext_links.append(ExtLink(link_id=link_count, ext_node=node,
146 int_node=routers[0],
147 latency = link_latency))
148
149 network.ext_links = ext_links
150
151 # Create the mesh links.
152 int_links = []
153
154 # East output to West input links (weight = 1)
155 for row in range(num_rows):
156 for col in range(num_columns):
157 if (col + 1 < num_columns):
158 east_out = col + (row * num_columns)
159 west_in = (col + 1) + (row * num_columns)
160 int_links.append(IntLink(link_id=link_count,
161 src_node=routers[east_out],
162 dst_node=routers[west_in],
163 src_outport="East",
164 dst_inport="West",
165 latency = link_latency,
166 weight=1))
167 link_count += 1
168
169 # West output to East input links (weight = 1)
170 for row in range(num_rows):
171 for col in range(num_columns):
172 if (col + 1 < num_columns):
173 east_in = col + (row * num_columns)
174 west_out = (col + 1) + (row * num_columns)
175 int_links.append(IntLink(link_id=link_count,
176 src_node=routers[west_out],
177 dst_node=routers[east_in],
178 src_outport="West",
179 dst_inport="East",
180 latency = link_latency,
181 weight=1))
182 link_count += 1
183
184 # North output to South input links (weight = 2)
185 for col in range(num_columns):
186 for row in range(num_rows):
187 if (row + 1 < num_rows):
188 north_out = col + (row * num_columns)
189 south_in = col + ((row + 1) * num_columns)
190 int_links.append(IntLink(link_id=link_count,
191 src_node=routers[north_out],
192 dst_node=routers[south_in],
193 src_outport="North",
194 dst_inport="South",
195 latency = link_latency,
196 weight=2))
197 link_count += 1
198
199 # South output to North input links (weight = 2)
200 for col in range(num_columns):
201 for row in range(num_rows):
202 if (row + 1 < num_rows):
203 north_in = col + (row * num_columns)
204 south_out = col + ((row + 1) * num_columns)
205 int_links.append(IntLink(link_id=link_count,
206 src_node=routers[south_out],
207 dst_node=routers[north_in],
208 src_outport="South",
209 dst_inport="North",
210 latency = link_latency,
211 weight=2))
212 link_count += 1
213
214
215 network.int_links = int_links
216
217 # Register nodes with filesystem
218 def registerTopology(self, options):
219 i = 0
220 for n in numa_nodes:
221 if n:
222 FileSystemConfig.register_node(n,
223 MemorySize(options.mem_size) / num_numa_nodes, i)
224 i += 1
225