1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Brad Beckmann
28
29from __future__ import print_function
30from __future__ import absolute_import
31
32from m5.params import *
33from m5.objects import *
34
35from .BaseTopology import SimpleTopology
36
37# Creates a Mesh topology with 4 directories, one at each corner.
38# One L1 (and L2, depending on the protocol) are connected to each router.
39# XY routing is enforced (using link weights) to guarantee deadlock freedom.
40
41class MeshDirCorners_XY(SimpleTopology):
42 description='MeshDirCorners_XY'
43
44 def __init__(self, controllers):
45 self.nodes = controllers
46
47 def makeTopology(self, options, network, IntLink, ExtLink, Router):
48 nodes = self.nodes
49
50 num_routers = options.num_cpus
51 num_rows = options.mesh_rows
52
53 # default values for link latency and router latency.
54 # Can be over-ridden on a per link/router basis
55 link_latency = options.link_latency # used by simple and garnet
56 router_latency = options.router_latency # only used by garnet
57
58
59 # First determine which nodes are cache cntrls vs. dirs vs. dma
60 cache_nodes = []
61 dir_nodes = []
62 dma_nodes = []
63 for node in nodes:
64 if node.type == 'L1Cache_Controller' or \
65 node.type == 'L2Cache_Controller':
66 cache_nodes.append(node)
67 elif node.type == 'Directory_Controller':
68 dir_nodes.append(node)
69 elif node.type == 'DMA_Controller':
70 dma_nodes.append(node)
71
72 # Obviously the number or rows must be <= the number of routers
73 # and evenly divisible. Also the number of caches must be a
74 # multiple of the number of routers and the number of directories
75 # must be four.
76 assert(num_rows > 0 and num_rows <= num_routers)
77 num_columns = int(num_routers / num_rows)
78 assert(num_columns * num_rows == num_routers)
79 caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
80 assert(remainder == 0)
81 assert(len(dir_nodes) == 4)
82
83 # Create the routers in the mesh
84 routers = [Router(router_id=i, latency = router_latency) \
85 for i in range(num_routers)]
86 network.routers = routers
87
88 # link counter to set unique link ids
89 link_count = 0
90
91 # Connect each cache controller to the appropriate router
92 ext_links = []
93 for (i, n) in enumerate(cache_nodes):
94 cntrl_level, router_id = divmod(i, num_routers)
95 assert(cntrl_level < caches_per_router)
96 ext_links.append(ExtLink(link_id=link_count, ext_node=n,
97 int_node=routers[router_id],
98 latency = link_latency))
99 link_count += 1
100
101 # Connect the dir nodes to the corners.
102 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
103 int_node=routers[0],
104 latency = link_latency))
105 link_count += 1
106 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1],
107 int_node=routers[num_columns - 1],
108 latency = link_latency))
109 link_count += 1
110 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2],
111 int_node=routers[num_routers - num_columns],
112 latency = link_latency))
113 link_count += 1
114 ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3],
115 int_node=routers[num_routers - 1],
116 latency = link_latency))
117 link_count += 1
118
119 # Connect the dma nodes to router 0. These should only be DMA nodes.
120 for (i, node) in enumerate(dma_nodes):
121 assert(node.type == 'DMA_Controller')
122 ext_links.append(ExtLink(link_id=link_count, ext_node=node,
123 int_node=routers[0],
124 latency = link_latency))
125
126 network.ext_links = ext_links
127
128 # Create the mesh links.
129 int_links = []
130
131 # East output to West input links (weight = 1)
132 for row in range(num_rows):
133 for col in range(num_columns):
134 if (col + 1 < num_columns):
135 east_out = col + (row * num_columns)
136 west_in = (col + 1) + (row * num_columns)
137 int_links.append(IntLink(link_id=link_count,
138 src_node=routers[east_out],
139 dst_node=routers[west_in],
140 src_outport="East",
141 dst_inport="West",
142 latency = link_latency,
143 weight=1))
144 link_count += 1
145
146 # West output to East input links (weight = 1)
147 for row in range(num_rows):
148 for col in range(num_columns):
149 if (col + 1 < num_columns):
150 east_in = col + (row * num_columns)
151 west_out = (col + 1) + (row * num_columns)
152 int_links.append(IntLink(link_id=link_count,
153 src_node=routers[west_out],
154 dst_node=routers[east_in],
155 src_outport="West",
156 dst_inport="East",
157 latency = link_latency,
158 weight=1))
159 link_count += 1
160
161 # North output to South input links (weight = 2)
162 for col in range(num_columns):
163 for row in range(num_rows):
164 if (row + 1 < num_rows):
165 north_out = col + (row * num_columns)
166 south_in = col + ((row + 1) * num_columns)
167 int_links.append(IntLink(link_id=link_count,
168 src_node=routers[north_out],
169 dst_node=routers[south_in],
170 src_outport="North",
171 dst_inport="South",
172 latency = link_latency,
173 weight=2))
174 link_count += 1
175
176 # South output to North input links (weight = 2)
177 for col in range(num_columns):
178 for row in range(num_rows):
179 if (row + 1 < num_rows):
180 north_in = col + (row * num_columns)
181 south_out = col + ((row + 1) * num_columns)
182 int_links.append(IntLink(link_id=link_count,
183 src_node=routers[south_out],
184 dst_node=routers[north_in],
185 src_outport="South",
186 dst_inport="North",
187 latency = link_latency,
188 weight=2))
189 link_count += 1
190
191
192 network.int_links = int_links