| run.py (9815:3b3b94536547) | run.py (10405:7a618c07e663) |
|---|---|
| 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 182 unchanged lines hidden (view full) --- 191 cpus = [AtomicSimpleCPU(cpu_id = i, 192 clock=options.frequency) 193 for i in xrange(options.numcpus)] 194 195# ---------------------- 196# Create a system, and add system wide objects 197# ---------------------- 198system = System(cpu = cpus, physmem = SimpleMemory(), | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 182 unchanged lines hidden (view full) --- 191 cpus = [AtomicSimpleCPU(cpu_id = i, 192 clock=options.frequency) 193 for i in xrange(options.numcpus)] 194 195# ---------------------- 196# Create a system, and add system wide objects 197# ---------------------- 198system = System(cpu = cpus, physmem = SimpleMemory(), |
| 199 membus = CoherentBus(clock = busFrequency)) | 199 membus = CoherentXBar(clock = busFrequency)) |
| 200system.clock = '1GHz' 201 | 200system.clock = '1GHz' 201 |
| 202system.toL2bus = CoherentBus(clock = busFrequency) | 202system.toL2bus = CoherentXBar(clock = busFrequency) |
| 203system.l2 = L2(size = options.l2size, assoc = 8) 204 205# ---------------------- 206# Connect the L2 cache and memory together 207# ---------------------- 208 209system.physmem.port = system.membus.master 210system.l2.cpu_side = system.toL2bus.master --- 77 unchanged lines hidden --- | 203system.l2 = L2(size = options.l2size, assoc = 8) 204 205# ---------------------- 206# Connect the L2 cache and memory together 207# ---------------------- 208 209system.physmem.port = system.membus.master 210system.l2.cpu_side = system.toL2bus.master --- 77 unchanged lines hidden --- |