| run.py (8801:1a84c6a81299) | run.py (8836:922edffe734d) |
|---|---|
| 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 196 unchanged lines hidden (view full) --- 205 206# ---------------------- 207# Connect the L2 cache and memory together 208# ---------------------- 209 210system.physmem.port = system.membus.port 211system.l2.cpu_side = system.toL2bus.port 212system.l2.mem_side = system.membus.port | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 196 unchanged lines hidden (view full) --- 205 206# ---------------------- 207# Connect the L2 cache and memory together 208# ---------------------- 209 210system.physmem.port = system.membus.port 211system.l2.cpu_side = system.toL2bus.port 212system.l2.mem_side = system.membus.port |
| 213system.system_port = system.membus.port |
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| 213 214# ---------------------- 215# Connect the L2 cache and clusters together 216# ---------------------- 217for cpu in cpus: 218 cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), 219 L1(size = options.l1size, assoc = 4)) 220 # connect cpu level-1 caches to shared level-2 cache --- 67 unchanged lines hidden --- | 214 215# ---------------------- 216# Connect the L2 cache and clusters together 217# ---------------------- 218for cpu in cpus: 219 cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), 220 L1(size = options.l1size, assoc = 4)) 221 # connect cpu level-1 caches to shared level-2 cache --- 67 unchanged lines hidden --- |