run.py (7525:722f2ad014a7) run.py (7716:fa706473bcd5)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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212system.l2.mem_side = system.membus.port
213
214# ----------------------
215# Connect the L2 cache and clusters together
216# ----------------------
217for cpu in cpus:
218 cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
219 L1(size = options.l1size, assoc = 4))
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 203 unchanged lines hidden (view full) ---

212system.l2.mem_side = system.membus.port
213
214# ----------------------
215# Connect the L2 cache and clusters together
216# ----------------------
217for cpu in cpus:
218 cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
219 L1(size = options.l1size, assoc = 4))
220 cpu.mem = cpu.dcache
221 # connect cpu level-1 caches to shared level-2 cache
222 cpu.connectMemPorts(system.toL2bus)
223
224
225# ----------------------
226# Define the root
227# ----------------------
228

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220 # connect cpu level-1 caches to shared level-2 cache
221 cpu.connectMemPorts(system.toL2bus)
222
223
224# ----------------------
225# Define the root
226# ----------------------
227

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