1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 184 unchanged lines hidden (view full) --- 193 cpus = [AtomicSimpleCPU(cpu_id = i, 194 clock=options.frequency) 195 for i in xrange(options.numcpus)] 196 197# ---------------------- 198# Create a system, and add system wide objects 199# ---------------------- 200system = System(cpu = cpus, physmem = SimpleMemory(), |
201 membus = CoherentBus(clock = busFrequency)) |
202 |
203system.toL2bus = CoherentBus(clock = busFrequency) |
204system.l2 = L2(size = options.l2size, assoc = 8) 205 206# ---------------------- 207# Connect the L2 cache and memory together 208# ---------------------- 209 210system.physmem.port = system.membus.master 211system.l2.cpu_side = system.toL2bus.master --- 77 unchanged lines hidden --- |