1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 204 unchanged lines hidden (view full) --- 213 214# ---------------------- 215# Connect the L2 cache and clusters together 216# ---------------------- 217for cpu in cpus: 218 cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), 219 L1(size = options.l1size, assoc = 4)) 220 # connect cpu level-1 caches to shared level-2 cache |
221 cpu.connectAllPorts(system.toL2bus, system.membus) |
222 223 224# ---------------------- 225# Define the root 226# ---------------------- 227 228root = Root(system = system) 229 --- 58 unchanged lines hidden --- |