| cluster.py (8847:ef8630054b5e) | cluster.py (8931:7a1dfb191e3f) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 197 unchanged lines hidden (view full) --- 206 for i in xrange(cpusPerCluster)] 207 all_cpus += cluster.cpus 208 cluster.l1 = L1(size=options.l1size, assoc = 4) 209 all_l1s += [cluster.l1] 210 211# ---------------------- 212# Create a system, and add system wide objects 213# ---------------------- | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 197 unchanged lines hidden (view full) --- 206 for i in xrange(cpusPerCluster)] 207 all_cpus += cluster.cpus 208 cluster.l1 = L1(size=options.l1size, assoc = 4) 209 all_l1s += [cluster.l1] 210 211# ---------------------- 212# Create a system, and add system wide objects 213# ---------------------- |
| 214system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem = PhysicalMemory(), 215 membus = Bus(clock = busFrequency)) | 214system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, 215 physmem = SimpleMemory(), membus = Bus(clock = busFrequency)) |
| 216 217system.toL2bus = Bus(clock = busFrequency) 218system.l2 = L2(size = options.l2size, assoc = 8) 219 220# ---------------------- 221# Connect the L2 cache and memory together 222# ---------------------- 223 --- 80 unchanged lines hidden --- | 216 217system.toL2bus = Bus(clock = busFrequency) 218system.l2 = L2(size = options.l2size, assoc = 8) 219 220# ---------------------- 221# Connect the L2 cache and memory together 222# ---------------------- 223 --- 80 unchanged lines hidden --- |