| cluster.py (8801:1a84c6a81299) | cluster.py (8847:ef8630054b5e) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 207 unchanged lines hidden (view full) --- 216 217system.toL2bus = Bus(clock = busFrequency) 218system.l2 = L2(size = options.l2size, assoc = 8) 219 220# ---------------------- 221# Connect the L2 cache and memory together 222# ---------------------- 223 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 207 unchanged lines hidden (view full) --- 216 217system.toL2bus = Bus(clock = busFrequency) 218system.l2 = L2(size = options.l2size, assoc = 8) 219 220# ---------------------- 221# Connect the L2 cache and memory together 222# ---------------------- 223 |
| 224system.physmem.port = system.membus.port 225system.l2.cpu_side = system.toL2bus.port 226system.l2.mem_side = system.membus.port | 224system.physmem.port = system.membus.master 225system.l2.cpu_side = system.toL2bus.slave 226system.l2.mem_side = system.membus.master |
| 227 228# ---------------------- 229# Connect the L2 cache and clusters together 230# ---------------------- 231for cluster in clusters: | 227 228# ---------------------- 229# Connect the L2 cache and clusters together 230# ---------------------- 231for cluster in clusters: |
| 232 cluster.l1.cpu_side = cluster.clusterbus.port 233 cluster.l1.mem_side = system.toL2bus.port | 232 cluster.l1.cpu_side = cluster.clusterbus.master 233 cluster.l1.mem_side = system.toL2bus.slave |
| 234 for cpu in cluster.cpus: | 234 for cpu in cluster.cpus: |
| 235 cpu.icache_port = cluster.clusterbus.port 236 cpu.dcache_port = cluster.clusterbus.port | 235 cpu.icache_port = cluster.clusterbus.slave 236 cpu.dcache_port = cluster.clusterbus.slave |
| 237 238# ---------------------- 239# Define the root 240# ---------------------- 241 242root = Root(full_system = False, system = system) 243 244# -------------------- --- 59 unchanged lines hidden --- | 237 238# ---------------------- 239# Define the root 240# ---------------------- 241 242root = Root(full_system = False, system = system) 243 244# -------------------- --- 59 unchanged lines hidden --- |