1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 159 unchanged lines hidden (view full) --- 168all_cpus = [] 169all_l1s = [] 170all_l1buses = [] 171if options.timing: 172 clusters = [ Cluster() for i in xrange(options.numclusters)] 173 for j in xrange(options.numclusters): 174 clusters[j].id = j 175 for cluster in clusters: |
176 cluster.clusterbus = CoherentBus(clock=busFrequency) |
177 all_l1buses += [cluster.clusterbus] 178 cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id, 179 clock=options.frequency) 180 for i in xrange(cpusPerCluster)] 181 all_cpus += cluster.cpus 182 cluster.l1 = L1(size=options.l1size, assoc = 4) 183 all_l1s += [cluster.l1] 184elif options.detailed: 185 clusters = [ Cluster() for i in xrange(options.numclusters)] 186 for j in xrange(options.numclusters): 187 clusters[j].id = j 188 for cluster in clusters: |
189 cluster.clusterbus = CoherentBus(clock=busFrequency) |
190 all_l1buses += [cluster.clusterbus] 191 cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id, 192 clock=options.frequency) 193 for i in xrange(cpusPerCluster)] 194 all_cpus += cluster.cpus 195 cluster.l1 = L1(size=options.l1size, assoc = 4) 196 all_l1s += [cluster.l1] 197else: 198 clusters = [ Cluster() for i in xrange(options.numclusters)] 199 for j in xrange(options.numclusters): 200 clusters[j].id = j 201 for cluster in clusters: |
202 cluster.clusterbus = CoherentBus(clock=busFrequency) |
203 all_l1buses += [cluster.clusterbus] 204 cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id, 205 clock=options.frequency) 206 for i in xrange(cpusPerCluster)] 207 all_cpus += cluster.cpus 208 cluster.l1 = L1(size=options.l1size, assoc = 4) 209 all_l1s += [cluster.l1] 210 211# ---------------------- 212# Create a system, and add system wide objects 213# ---------------------- 214system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, |
215 physmem = SimpleMemory(), 216 membus = CoherentBus(clock = busFrequency)) |
217 |
218system.toL2bus = CoherentBus(clock = busFrequency) |
219system.l2 = L2(size = options.l2size, assoc = 8) 220 221# ---------------------- 222# Connect the L2 cache and memory together 223# ---------------------- 224 225system.physmem.port = system.membus.master 226system.l2.cpu_side = system.toL2bus.slave --- 78 unchanged lines hidden --- |