1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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209 all_l1s += [cluster.l1]
210
211# ----------------------
212# Create a system, and add system wide objects
213# ----------------------
214system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
215 physmem = SimpleMemory(),
216 membus = CoherentBus(clock = busFrequency))
217system.clock = '1GHz'
218
219system.toL2bus = CoherentBus(clock = busFrequency)
220system.l2 = L2(size = options.l2size, assoc = 8)
221
222# ----------------------
223# Connect the L2 cache and memory together
224# ----------------------
225

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