| Ruby.py (11046:0cd13910b063) | Ruby.py (11049:dfb0aa3f0649) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 68 unchanged lines hidden (view full) --- 77 # ruby mapping options 78 parser.add_option("--numa-high-bit", type="int", default=0, 79 help="high order address bit to use for numa mapping. " \ 80 "0 = highest bit, not specified = lowest bit") 81 82 parser.add_option("--recycle-latency", type="int", default=10, 83 help="Recycle latency for ruby controller input buffers") 84 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 68 unchanged lines hidden (view full) --- 77 # ruby mapping options 78 parser.add_option("--numa-high-bit", type="int", default=0, 79 help="high order address bit to use for numa mapping. " \ 80 "0 = highest bit, not specified = lowest bit") 81 82 parser.add_option("--recycle-latency", type="int", default=10, 83 help="Recycle latency for ruby controller input buffers") 84 |
| 85 parser.add_option("--random_seed", type="int", default=1234, 86 help="Used for seeding the random number generator") 87 |
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| 85 protocol = buildEnv['PROTOCOL'] 86 exec "import %s" % protocol 87 eval("%s.define_options(parser)" % protocol) 88 89def setup_memory_controllers(system, ruby, dir_cntrls, options): 90 ruby.block_size_bytes = options.cacheline_size 91 ruby.memory_size_bits = 48 92 block_size_bits = int(math.log(options.cacheline_size, 2)) --- 133 unchanged lines hidden (view full) --- 226 if piobus != None: 227 for cpu_seq in cpu_sequencers: 228 cpu_seq.pio_master_port = piobus.slave 229 cpu_seq.mem_master_port = piobus.slave 230 231 if buildEnv['TARGET_ISA'] == "x86": 232 cpu_seq.pio_slave_port = piobus.master 233 | 88 protocol = buildEnv['PROTOCOL'] 89 exec "import %s" % protocol 90 eval("%s.define_options(parser)" % protocol) 91 92def setup_memory_controllers(system, ruby, dir_cntrls, options): 93 ruby.block_size_bytes = options.cacheline_size 94 ruby.memory_size_bits = 48 95 block_size_bits = int(math.log(options.cacheline_size, 2)) --- 133 unchanged lines hidden (view full) --- 229 if piobus != None: 230 for cpu_seq in cpu_sequencers: 231 cpu_seq.pio_master_port = piobus.slave 232 cpu_seq.mem_master_port = piobus.slave 233 234 if buildEnv['TARGET_ISA'] == "x86": 235 cpu_seq.pio_slave_port = piobus.master 236 |
| 234 ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks | |
| 235 ruby._cpu_ports = cpu_sequencers 236 ruby.num_of_sequencers = len(cpu_sequencers) | 237 ruby._cpu_ports = cpu_sequencers 238 ruby.num_of_sequencers = len(cpu_sequencers) |
| 239 ruby.random_seed = options.random_seed |
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| 237 238 # Create a backing copy of physical memory in case required 239 if options.access_backing_store: 240 ruby.access_backing_store = True 241 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 242 in_addr_map=False) 243 244def send_evicts(options): 245 # currently, 2 scenarios warrant forwarding evictions to the CPU: 246 # 1. The O3 model must keep the LSQ coherent with the caches 247 # 2. The x86 mwait instruction is built on top of coherence invalidations 248 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 249 return True 250 return False | 240 241 # Create a backing copy of physical memory in case required 242 if options.access_backing_store: 243 ruby.access_backing_store = True 244 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 245 in_addr_map=False) 246 247def send_evicts(options): 248 # currently, 2 scenarios warrant forwarding evictions to the CPU: 249 # 1. The O3 model must keep the LSQ coherent with the caches 250 # 2. The x86 mwait instruction is built on top of coherence invalidations 251 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 252 return True 253 return False |