| Ruby.py (10706:4206946d60fe) | Ruby.py (10720:67b3e74de9ae) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 102 unchanged lines hidden (view full) --- 111 # attached to a directory controller. A separate controller is created 112 # for each address range as the abstract memory can handle only one 113 # contiguous address range as of now. 114 for dir_cntrl in dir_cntrls: 115 dir_cntrl.directory.numa_high_bit = numa_bit 116 117 crossbar = None 118 if len(system.mem_ranges) > 1: | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 102 unchanged lines hidden (view full) --- 111 # attached to a directory controller. A separate controller is created 112 # for each address range as the abstract memory can handle only one 113 # contiguous address range as of now. 114 for dir_cntrl in dir_cntrls: 115 dir_cntrl.directory.numa_high_bit = numa_bit 116 117 crossbar = None 118 if len(system.mem_ranges) > 1: |
| 119 crossbar = NoncoherentXBar() | 119 crossbar = IOXBar() |
| 120 crossbars.append(crossbar) 121 dir_cntrl.memory = crossbar.slave 122 123 for r in system.mem_ranges: 124 mem_ctrl = MemConfig.create_mem_ctrl( 125 MemConfig.get(options.mem_type), r, index, options.num_dirs, 126 int(math.log(options.num_dirs, 2)), options.cacheline_size) 127 --- 121 unchanged lines hidden --- | 120 crossbars.append(crossbar) 121 dir_cntrl.memory = crossbar.slave 122 123 for r in system.mem_ranges: 124 mem_ctrl = MemConfig.create_mem_ctrl( 125 MemConfig.get(options.mem_type), r, index, options.num_dirs, 126 int(math.log(options.num_dirs, 2)), options.cacheline_size) 127 --- 121 unchanged lines hidden --- |