| Ruby.py (10551:d60a9bb99038) | Ruby.py (10630:64618b7c57b2) |
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| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 219 unchanged lines hidden (view full) --- 228 229 if buildEnv['TARGET_ISA'] == "x86": 230 cpu_seq.pio_slave_port = piobus.master 231 232 ruby._cpu_ports = cpu_sequencers 233 ruby.num_of_sequencers = len(cpu_sequencers) 234 ruby.random_seed = options.random_seed 235 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 219 unchanged lines hidden (view full) --- 228 229 if buildEnv['TARGET_ISA'] == "x86": 230 cpu_seq.pio_slave_port = piobus.master 231 232 ruby._cpu_ports = cpu_sequencers 233 ruby.num_of_sequencers = len(cpu_sequencers) 234 ruby.random_seed = options.random_seed 235 |
| 236 # Create a backing copy of physical memory in case required 237 if options.access_backing_store: 238 ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 239 in_addr_map=False) 240 |
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| 236def send_evicts(options): 237 # currently, 2 scenarios warrant forwarding evictions to the CPU: 238 # 1. The O3 model must keep the LSQ coherent with the caches 239 # 2. The x86 mwait instruction is built on top of coherence invalidations 240 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 241 return True 242 return False | 241def send_evicts(options): 242 # currently, 2 scenarios warrant forwarding evictions to the CPU: 243 # 1. The O3 model must keep the LSQ coherent with the caches 244 # 2. The x86 mwait instruction is built on top of coherence invalidations 245 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 246 return True 247 return False |
| 243 244 # Create a backing copy of physical memory in case required 245 if options.access_backing_store: 246 ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 247 in_addr_map=False) | |