| Ruby.py (10524:fff17530cef6) | Ruby.py (10525:77787650cbbc) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 42 unchanged lines hidden (view full) --- 51def define_options(parser): 52 # By default, ruby uses the simple timing cpu 53 parser.set_defaults(cpu_type="timing") 54 55 parser.add_option("--ruby-clock", action="store", type="string", 56 default='2GHz', 57 help="Clock for blocks running at Ruby system's speed") 58 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 42 unchanged lines hidden (view full) --- 51def define_options(parser): 52 # By default, ruby uses the simple timing cpu 53 parser.set_defaults(cpu_type="timing") 54 55 parser.add_option("--ruby-clock", action="store", type="string", 56 default='2GHz', 57 help="Clock for blocks running at Ruby system's speed") 58 |
| 59 parser.add_option("--access-backing-store", action="store_true", default=False, 60 help="Should ruby maintain a second copy of memory") 61 |
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| 59 # Options related to cache structure 60 parser.add_option("--ports", action="store", type="int", default=4, 61 help="used of transitions per cycle which is a proxy \ 62 for the number of ports.") 63 64 # ruby network options 65 parser.add_option("--topology", type="string", default="Crossbar", 66 help="check src/mem/ruby/network/topologies for complete set") --- 157 unchanged lines hidden (view full) --- 224 cpu_seq.mem_master_port = piobus.slave 225 226 if buildEnv['TARGET_ISA'] == "x86": 227 cpu_seq.pio_slave_port = piobus.master 228 229 ruby._cpu_ports = cpu_sequencers 230 ruby.num_of_sequencers = len(cpu_sequencers) 231 ruby.random_seed = options.random_seed | 62 # Options related to cache structure 63 parser.add_option("--ports", action="store", type="int", default=4, 64 help="used of transitions per cycle which is a proxy \ 65 for the number of ports.") 66 67 # ruby network options 68 parser.add_option("--topology", type="string", default="Crossbar", 69 help="check src/mem/ruby/network/topologies for complete set") --- 157 unchanged lines hidden (view full) --- 227 cpu_seq.mem_master_port = piobus.slave 228 229 if buildEnv['TARGET_ISA'] == "x86": 230 cpu_seq.pio_slave_port = piobus.master 231 232 ruby._cpu_ports = cpu_sequencers 233 ruby.num_of_sequencers = len(cpu_sequencers) 234 ruby.random_seed = options.random_seed |
| 235 236 # Create a backing copy of physical memory in case required 237 if options.access_backing_store: 238 ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 239 in_addr_map=False) |
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