| Ruby.py (10122:1268f1fd2714) | Ruby.py (10311:ad9c042dce54) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 92 unchanged lines hidden (view full) --- 101 topology = eval("Topo.%s(controllers)" % options.topology) 102 return topology 103 104def create_system(options, system, piobus = None, dma_ports = []): 105 106 system.ruby = RubySystem(no_mem_vec = options.use_map) 107 ruby = system.ruby 108 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 92 unchanged lines hidden (view full) --- 101 topology = eval("Topo.%s(controllers)" % options.topology) 102 return topology 103 104def create_system(options, system, piobus = None, dma_ports = []): 105 106 system.ruby = RubySystem(no_mem_vec = options.use_map) 107 ruby = system.ruby 108 |
| 109 protocol = buildEnv['PROTOCOL'] 110 exec "import %s" % protocol 111 try: 112 (cpu_sequencers, dir_cntrls, topology) = \ 113 eval("%s.create_system(options, system, dma_ports, ruby)" 114 % protocol) 115 except: 116 print "Error: could not create sytem for ruby protocol %s" % protocol 117 raise 118 119 # Create a port proxy for connecting the system port. This is 120 # independent of the protocol and kept in the protocol-agnostic 121 # part (i.e. here). 122 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 123 # Give the system port proxy a SimObject parent without creating a 124 # full-fledged controller 125 system.sys_port_proxy = sys_port_proxy 126 127 # Connect the system port for loading of binaries etc 128 system.system_port = system.sys_port_proxy.slave 129 130 131 # | |
| 132 # Set the network classes based on the command line options | 109 # Set the network classes based on the command line options |
| 133 # | |
| 134 if options.garnet_network == "fixed": 135 NetworkClass = GarnetNetwork_d 136 IntLinkClass = GarnetIntLink_d 137 ExtLinkClass = GarnetExtLink_d 138 RouterClass = GarnetRouter_d 139 InterfaceClass = GarnetNetworkInterface_d 140 141 elif options.garnet_network == "flexible": --- 5 unchanged lines hidden (view full) --- 147 148 else: 149 NetworkClass = SimpleNetwork 150 IntLinkClass = SimpleIntLink 151 ExtLinkClass = SimpleExtLink 152 RouterClass = Switch 153 InterfaceClass = None 154 | 110 if options.garnet_network == "fixed": 111 NetworkClass = GarnetNetwork_d 112 IntLinkClass = GarnetIntLink_d 113 ExtLinkClass = GarnetExtLink_d 114 RouterClass = GarnetRouter_d 115 InterfaceClass = GarnetNetworkInterface_d 116 117 elif options.garnet_network == "flexible": --- 5 unchanged lines hidden (view full) --- 123 124 else: 125 NetworkClass = SimpleNetwork 126 IntLinkClass = SimpleIntLink 127 ExtLinkClass = SimpleExtLink 128 RouterClass = Switch 129 InterfaceClass = None 130 |
| 131 # Instantiate the network object so that the controllers can connect to it. 132 network = NetworkClass(ruby_system = ruby, topology = options.topology, 133 routers = [], ext_links = [], int_links = [], netifs = []) 134 ruby.network = network |
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| 155 | 135 |
| 136 protocol = buildEnv['PROTOCOL'] 137 exec "import %s" % protocol 138 try: 139 (cpu_sequencers, dir_cntrls, topology) = \ 140 eval("%s.create_system(options, system, dma_ports, ruby)" 141 % protocol) 142 except: 143 print "Error: could not create sytem for ruby protocol %s" % protocol 144 raise 145 146 # Create a port proxy for connecting the system port. This is 147 # independent of the protocol and kept in the protocol-agnostic 148 # part (i.e. here). 149 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 150 151 # Give the system port proxy a SimObject parent without creating a 152 # full-fledged controller 153 system.sys_port_proxy = sys_port_proxy 154 155 # Connect the system port for loading of binaries etc 156 system.system_port = system.sys_port_proxy.slave 157 |
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| 156 # Create the network topology | 158 # Create the network topology |
| 157 network = NetworkClass(ruby_system = ruby, topology = topology.description, 158 routers = [], ext_links = [], int_links = [], netifs = []) | |
| 159 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 160 RouterClass) 161 162 if InterfaceClass != None: 163 netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 164 network.netifs = netifs 165 166 if options.network_fault_model: 167 assert(options.garnet_network == "fixed") 168 network.enable_fault_model = True 169 network.fault_model = FaultModel() 170 | 159 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 160 RouterClass) 161 162 if InterfaceClass != None: 163 netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 164 network.netifs = netifs 165 166 if options.network_fault_model: 167 assert(options.garnet_network == "fixed") 168 network.enable_fault_model = True 169 network.fault_model = FaultModel() 170 |
| 171 # | |
| 172 # Loop through the directory controlers. 173 # Determine the total memory size of the ruby system and verify it is equal 174 # to physmem. However, if Ruby memory is using sparse memory in SE 175 # mode, then the system should not back-up the memory state with 176 # the Memory Vector and thus the memory size bytes should stay at 0. 177 # Also set the numa bits to the appropriate values. | 171 # Loop through the directory controlers. 172 # Determine the total memory size of the ruby system and verify it is equal 173 # to physmem. However, if Ruby memory is using sparse memory in SE 174 # mode, then the system should not back-up the memory state with 175 # the Memory Vector and thus the memory size bytes should stay at 0. 176 # Also set the numa bits to the appropriate values. |
| 178 # | |
| 179 total_mem_size = MemorySize('0B') 180 181 ruby.block_size_bytes = options.cacheline_size 182 block_size_bits = int(math.log(options.cacheline_size, 2)) 183 184 if options.numa_high_bit: 185 numa_bit = options.numa_high_bit 186 else: --- 4 unchanged lines hidden (view full) --- 191 numa_bit = block_size_bits + dir_bits - 1 192 193 for dir_cntrl in dir_cntrls: 194 total_mem_size.value += dir_cntrl.directory.size.value 195 dir_cntrl.directory.numa_high_bit = numa_bit 196 197 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 198 assert(total_mem_size.value == phys_mem_size) | 177 total_mem_size = MemorySize('0B') 178 179 ruby.block_size_bytes = options.cacheline_size 180 block_size_bits = int(math.log(options.cacheline_size, 2)) 181 182 if options.numa_high_bit: 183 numa_bit = options.numa_high_bit 184 else: --- 4 unchanged lines hidden (view full) --- 189 numa_bit = block_size_bits + dir_bits - 1 190 191 for dir_cntrl in dir_cntrls: 192 total_mem_size.value += dir_cntrl.directory.size.value 193 dir_cntrl.directory.numa_high_bit = numa_bit 194 195 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 196 assert(total_mem_size.value == phys_mem_size) |
| 199 200 ruby.network = network | |
| 201 ruby.mem_size = total_mem_size 202 203 # Connect the cpu sequencers and the piobus 204 if piobus != None: 205 for cpu_seq in cpu_sequencers: 206 cpu_seq.pio_master_port = piobus.slave 207 cpu_seq.mem_master_port = piobus.slave 208 209 if buildEnv['TARGET_ISA'] == "x86": 210 cpu_seq.pio_slave_port = piobus.master 211 212 ruby._cpu_ports = cpu_sequencers 213 ruby.num_of_sequencers = len(cpu_sequencers) 214 ruby.random_seed = options.random_seed | 197 ruby.mem_size = total_mem_size 198 199 # Connect the cpu sequencers and the piobus 200 if piobus != None: 201 for cpu_seq in cpu_sequencers: 202 cpu_seq.pio_master_port = piobus.slave 203 cpu_seq.mem_master_port = piobus.slave 204 205 if buildEnv['TARGET_ISA'] == "x86": 206 cpu_seq.pio_slave_port = piobus.master 207 208 ruby._cpu_ports = cpu_sequencers 209 ruby.num_of_sequencers = len(cpu_sequencers) 210 ruby.random_seed = options.random_seed |