1# Copyright (c) 2012, 2017 ARM Limited
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1# Copyright (c) 2012, 2017-2018 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# Copyright (c) 2009 Advanced Micro Devices, Inc. 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Brad Beckmann 41 42from __future__ import print_function 43 44import math 45import m5 46from m5.objects import * 47from m5.defines import buildEnv 48from m5.util import addToPath, fatal 49 50from common import MemConfig 51 52from topologies import * 53from network import Network 54 55def define_options(parser): 56 # By default, ruby uses the simple timing cpu 57 parser.set_defaults(cpu_type="TimingSimpleCPU") 58 59 parser.add_option("--ruby-clock", action="store", type="string", 60 default='2GHz', 61 help="Clock for blocks running at Ruby system's speed") 62 63 parser.add_option("--access-backing-store", action="store_true", default=False, 64 help="Should ruby maintain a second copy of memory") 65 66 # Options related to cache structure 67 parser.add_option("--ports", action="store", type="int", default=4, 68 help="used of transitions per cycle which is a proxy \ 69 for the number of ports.") 70 71 # network options are in network/Network.py 72 73 # ruby mapping options 74 parser.add_option("--numa-high-bit", type="int", default=0, 75 help="high order address bit to use for numa mapping. " \ 76 "0 = highest bit, not specified = lowest bit") 77 78 parser.add_option("--recycle-latency", type="int", default=10, 79 help="Recycle latency for ruby controller input buffers") 80 81 protocol = buildEnv['PROTOCOL'] 82 exec "import %s" % protocol 83 eval("%s.define_options(parser)" % protocol) 84 Network.define_options(parser) 85 86def setup_memory_controllers(system, ruby, dir_cntrls, options): 87 ruby.block_size_bytes = options.cacheline_size 88 ruby.memory_size_bits = 48 89 90 index = 0 91 mem_ctrls = [] 92 crossbars = [] 93 94 # Sets bits to be used for interleaving. Creates memory controllers 95 # attached to a directory controller. A separate controller is created 96 # for each address range as the abstract memory can handle only one 97 # contiguous address range as of now. 98 for dir_cntrl in dir_cntrls: 99 crossbar = None 100 if len(system.mem_ranges) > 1: 101 crossbar = IOXBar() 102 crossbars.append(crossbar) 103 dir_cntrl.memory = crossbar.slave 104 105 for r in system.mem_ranges: 106 mem_ctrl = MemConfig.create_mem_ctrl( 107 MemConfig.get(options.mem_type), r, index, options.num_dirs, 108 int(math.log(options.num_dirs, 2)), options.cacheline_size) 109 110 if options.access_backing_store: 111 mem_ctrl.kvm_map=False 112 113 mem_ctrls.append(mem_ctrl) 114 115 if crossbar != None: 116 mem_ctrl.port = crossbar.master 117 else: 118 mem_ctrl.port = dir_cntrl.memory 119 120 index += 1 121 122 system.mem_ctrls = mem_ctrls 123 124 if len(crossbars) > 0: 125 ruby.crossbars = crossbars 126 127 128def create_topology(controllers, options): 129 """ Called from create_system in configs/ruby/<protocol>.py 130 Must return an object which is a subclass of BaseTopology 131 found in configs/topologies/BaseTopology.py 132 This is a wrapper for the legacy topologies. 133 """ 134 exec "import topologies.%s as Topo" % options.topology 135 topology = eval("Topo.%s(controllers)" % options.topology) 136 return topology 137
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138def create_system(options, full_system, system, piobus = None, dma_ports = []):
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138def create_system(options, full_system, system, piobus = None, dma_ports = [], 139 bootmem=None): |
140 141 system.ruby = RubySystem() 142 ruby = system.ruby 143 144 # Create the network object 145 (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 146 Network.create_network(options, ruby) 147 ruby.network = network 148 149 protocol = buildEnv['PROTOCOL'] 150 exec "import %s" % protocol 151 try: 152 (cpu_sequencers, dir_cntrls, topology) = \ 153 eval("%s.create_system(options, full_system, system, dma_ports,\
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153 ruby)"
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154 bootmem, ruby)" |
155 % protocol) 156 except: 157 print("Error: could not create sytem for ruby protocol %s" % protocol) 158 raise 159 160 # Create the network topology 161 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 162 RouterClass) 163 164 # Initialize network based on topology 165 Network.init_network(options, network, InterfaceClass) 166 167 # Create a port proxy for connecting the system port. This is 168 # independent of the protocol and kept in the protocol-agnostic 169 # part (i.e. here). 170 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 171 if piobus is not None: 172 sys_port_proxy.pio_master_port = piobus.slave 173 174 # Give the system port proxy a SimObject parent without creating a 175 # full-fledged controller 176 system.sys_port_proxy = sys_port_proxy 177 178 # Connect the system port for loading of binaries etc 179 system.system_port = system.sys_port_proxy.slave 180 181 setup_memory_controllers(system, ruby, dir_cntrls, options) 182 183 # Connect the cpu sequencers and the piobus 184 if piobus != None: 185 for cpu_seq in cpu_sequencers: 186 cpu_seq.pio_master_port = piobus.slave 187 cpu_seq.mem_master_port = piobus.slave 188 189 if buildEnv['TARGET_ISA'] == "x86": 190 cpu_seq.pio_slave_port = piobus.master 191 192 ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 193 ruby._cpu_ports = cpu_sequencers 194 ruby.num_of_sequencers = len(cpu_sequencers) 195 196 # Create a backing copy of physical memory in case required 197 if options.access_backing_store: 198 ruby.access_backing_store = True 199 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 200 in_addr_map=False) 201
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201def create_directories(options, mem_ranges, ruby_system):
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202def create_directories(options, mem_ranges, bootmem, ruby_system, 203 system): |
204 dir_cntrl_nodes = [] 205 if options.numa_high_bit: 206 numa_bit = options.numa_high_bit 207 else: 208 # if the numa_bit is not specified, set the directory bits as the 209 # lowest bits above the block offset bits, and the numa_bit as the 210 # highest of those directory bits 211 dir_bits = int(math.log(options.num_dirs, 2)) 212 block_size_bits = int(math.log(options.cacheline_size, 2)) 213 numa_bit = block_size_bits + dir_bits - 1 214 215 for i in xrange(options.num_dirs): 216 dir_ranges = [] 217 for r in mem_ranges: 218 addr_range = m5.objects.AddrRange(r.start, size = r.size(), 219 intlvHighBit = numa_bit, 220 intlvBits = dir_bits, 221 intlvMatch = i) 222 dir_ranges.append(addr_range) 223 224 dir_cntrl = Directory_Controller() 225 dir_cntrl.version = i 226 dir_cntrl.directory = RubyDirectoryMemory() 227 dir_cntrl.ruby_system = ruby_system 228 dir_cntrl.addr_ranges = dir_ranges 229 230 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 231 dir_cntrl_nodes.append(dir_cntrl)
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230 return dir_cntrl_nodes
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232
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233 if bootmem is not None: 234 rom_dir_cntrl = Directory_Controller() 235 rom_dir_cntrl.directory = RubyDirectoryMemory() 236 rom_dir_cntrl.ruby_system = ruby_system 237 rom_dir_cntrl.version = i + 1 238 rom_dir_cntrl.memory = bootmem.port 239 rom_dir_cntrl.addr_ranges = bootmem.range 240 return (dir_cntrl_nodes, rom_dir_cntrl) 241 242 return (dir_cntrl_nodes, None) 243 |
244def send_evicts(options): 245 # currently, 2 scenarios warrant forwarding evictions to the CPU: 246 # 1. The O3 model must keep the LSQ coherent with the caches 247 # 2. The x86 mwait instruction is built on top of coherence invalidations 248 # 3. The local exclusive monitor in ARM systems 249 if options.cpu_type == "DerivO3CPU" or \ 250 buildEnv['TARGET_ISA'] in ('x86', 'arm'): 251 return True 252 return False
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