1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# Copyright (c) 2009 Advanced Micro Devices, Inc. 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Brad Beckmann 41 42import math 43import m5 44from m5.objects import * 45from m5.defines import buildEnv 46from m5.util import addToPath, fatal 47
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49 50from topologies import * 51from network import Network 52 53def define_options(parser): 54 # By default, ruby uses the simple timing cpu 55 parser.set_defaults(cpu_type="timing") 56 57 parser.add_option("--ruby-clock", action="store", type="string", 58 default='2GHz', 59 help="Clock for blocks running at Ruby system's speed") 60 61 parser.add_option("--access-backing-store", action="store_true", default=False, 62 help="Should ruby maintain a second copy of memory") 63 64 # Options related to cache structure 65 parser.add_option("--ports", action="store", type="int", default=4, 66 help="used of transitions per cycle which is a proxy \ 67 for the number of ports.") 68 69 # network options are in network/Network.py 70 71 # ruby mapping options 72 parser.add_option("--numa-high-bit", type="int", default=0, 73 help="high order address bit to use for numa mapping. " \ 74 "0 = highest bit, not specified = lowest bit") 75 76 parser.add_option("--recycle-latency", type="int", default=10, 77 help="Recycle latency for ruby controller input buffers") 78 79 protocol = buildEnv['PROTOCOL'] 80 exec "import %s" % protocol 81 eval("%s.define_options(parser)" % protocol) 82 Network.define_options(parser) 83 84def setup_memory_controllers(system, ruby, dir_cntrls, options): 85 ruby.block_size_bytes = options.cacheline_size 86 ruby.memory_size_bits = 48 87 block_size_bits = int(math.log(options.cacheline_size, 2)) 88 89 if options.numa_high_bit: 90 numa_bit = options.numa_high_bit 91 else: 92 # if the numa_bit is not specified, set the directory bits as the 93 # lowest bits above the block offset bits, and the numa_bit as the 94 # highest of those directory bits 95 dir_bits = int(math.log(options.num_dirs, 2)) 96 numa_bit = block_size_bits + dir_bits - 1 97 98 index = 0 99 mem_ctrls = [] 100 crossbars = [] 101 102 # Sets bits to be used for interleaving. Creates memory controllers 103 # attached to a directory controller. A separate controller is created 104 # for each address range as the abstract memory can handle only one 105 # contiguous address range as of now. 106 for dir_cntrl in dir_cntrls: 107 dir_cntrl.directory.numa_high_bit = numa_bit 108 109 crossbar = None 110 if len(system.mem_ranges) > 1: 111 crossbar = IOXBar() 112 crossbars.append(crossbar) 113 dir_cntrl.memory = crossbar.slave 114 115 for r in system.mem_ranges: 116 mem_ctrl = MemConfig.create_mem_ctrl( 117 MemConfig.get(options.mem_type), r, index, options.num_dirs, 118 int(math.log(options.num_dirs, 2)), options.cacheline_size) 119 120 if options.access_backing_store: 121 mem_ctrl.kvm_map=False 122 123 mem_ctrls.append(mem_ctrl) 124 125 if crossbar != None: 126 mem_ctrl.port = crossbar.master 127 else: 128 mem_ctrl.port = dir_cntrl.memory 129 130 index += 1 131 132 system.mem_ctrls = mem_ctrls 133 134 if len(crossbars) > 0: 135 ruby.crossbars = crossbars 136 137 138def create_topology(controllers, options): 139 """ Called from create_system in configs/ruby/<protocol>.py 140 Must return an object which is a subclass of BaseTopology 141 found in configs/topologies/BaseTopology.py 142 This is a wrapper for the legacy topologies. 143 """ 144 exec "import topologies.%s as Topo" % options.topology 145 topology = eval("Topo.%s(controllers)" % options.topology) 146 return topology 147 148def create_system(options, full_system, system, piobus = None, dma_ports = []): 149 150 system.ruby = RubySystem() 151 ruby = system.ruby 152 153 # Create the network object 154 (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 155 Network.create_network(options, ruby) 156 ruby.network = network 157 158 protocol = buildEnv['PROTOCOL'] 159 exec "import %s" % protocol 160 try: 161 (cpu_sequencers, dir_cntrls, topology) = \ 162 eval("%s.create_system(options, full_system, system, dma_ports,\ 163 ruby)" 164 % protocol) 165 except: 166 print "Error: could not create sytem for ruby protocol %s" % protocol 167 raise 168 169 # Create the network topology 170 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 171 RouterClass) 172 173 # Initialize network based on topology 174 Network.init_network(options, network, InterfaceClass) 175 176 # Create a port proxy for connecting the system port. This is 177 # independent of the protocol and kept in the protocol-agnostic 178 # part (i.e. here). 179 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 180 if piobus is not None: 181 sys_port_proxy.pio_master_port = piobus.slave 182 183 # Give the system port proxy a SimObject parent without creating a 184 # full-fledged controller 185 system.sys_port_proxy = sys_port_proxy 186 187 # Connect the system port for loading of binaries etc 188 system.system_port = system.sys_port_proxy.slave 189 190 setup_memory_controllers(system, ruby, dir_cntrls, options) 191 192 # Connect the cpu sequencers and the piobus 193 if piobus != None: 194 for cpu_seq in cpu_sequencers: 195 cpu_seq.pio_master_port = piobus.slave 196 cpu_seq.mem_master_port = piobus.slave 197 198 if buildEnv['TARGET_ISA'] == "x86": 199 cpu_seq.pio_slave_port = piobus.master 200 201 ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 202 ruby._cpu_ports = cpu_sequencers 203 ruby.num_of_sequencers = len(cpu_sequencers) 204 205 # Create a backing copy of physical memory in case required 206 if options.access_backing_store: 207 ruby.access_backing_store = True 208 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 209 in_addr_map=False) 210 211def send_evicts(options): 212 # currently, 2 scenarios warrant forwarding evictions to the CPU: 213 # 1. The O3 model must keep the LSQ coherent with the caches 214 # 2. The x86 mwait instruction is built on top of coherence invalidations 215 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 216 return True 217 return False
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