1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# Copyright (c) 2009 Advanced Micro Devices, Inc. 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Brad Beckmann 41 42import math 43import m5 44from m5.objects import * 45from m5.defines import buildEnv 46from m5.util import addToPath, fatal 47 48addToPath('../topologies') 49 50def define_options(parser): 51 # By default, ruby uses the simple timing cpu 52 parser.set_defaults(cpu_type="timing") 53 54 parser.add_option("--ruby-clock", action="store", type="string", 55 default='2GHz', 56 help="Clock for blocks running at Ruby system's speed") 57 58 # Options related to cache structure 59 parser.add_option("--ports", action="store", type="int", default=4, 60 help="used of transitions per cycle which is a proxy \ 61 for the number of ports.") 62 63 # ruby network options 64 parser.add_option("--topology", type="string", default="Crossbar", 65 help="check src/mem/ruby/network/topologies for complete set") 66 parser.add_option("--mesh-rows", type="int", default=1, 67 help="the number of rows in the mesh topology") 68 parser.add_option("--garnet-network", type="choice", 69 choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 70 parser.add_option("--network-fault-model", action="store_true", default=False, 71 help="enable network fault model: see src/mem/ruby/network/fault_model/") 72 73 # ruby mapping options 74 parser.add_option("--numa-high-bit", type="int", default=0, 75 help="high order address bit to use for numa mapping. " \ 76 "0 = highest bit, not specified = lowest bit") 77 78 # ruby sparse memory options 79 parser.add_option("--use-map", action="store_true", default=False) 80 parser.add_option("--map-levels", type="int", default=4) 81 82 parser.add_option("--recycle-latency", type="int", default=10, 83 help="Recycle latency for ruby controller input buffers") 84 85 parser.add_option("--random_seed", type="int", default=1234, 86 help="Used for seeding the random number generator") 87 88 parser.add_option("--ruby_stats", type="string", default="ruby.stats") 89 90 protocol = buildEnv['PROTOCOL'] 91 exec "import %s" % protocol 92 eval("%s.define_options(parser)" % protocol) 93 94def create_topology(controllers, options): 95 """ Called from create_system in configs/ruby/<protocol>.py 96 Must return an object which is a subclass of BaseTopology 97 found in configs/topologies/BaseTopology.py 98 This is a wrapper for the legacy topologies. 99 """ 100 exec "import %s as Topo" % options.topology 101 topology = eval("Topo.%s(controllers)" % options.topology) 102 return topology 103
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142 % protocol) 143 except: 144 print "Error: could not create sytem for ruby protocol %s" % protocol 145 raise 146 147 # Create a port proxy for connecting the system port. This is 148 # independent of the protocol and kept in the protocol-agnostic 149 # part (i.e. here). 150 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 151 152 # Give the system port proxy a SimObject parent without creating a 153 # full-fledged controller 154 system.sys_port_proxy = sys_port_proxy 155 156 # Connect the system port for loading of binaries etc 157 system.system_port = system.sys_port_proxy.slave 158 159 # Create the network topology 160 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 161 RouterClass) 162 163 if InterfaceClass != None: 164 netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 165 network.netifs = netifs 166 167 if options.network_fault_model: 168 assert(options.garnet_network == "fixed") 169 network.enable_fault_model = True 170 network.fault_model = FaultModel() 171 172 # Loop through the directory controlers. 173 # Determine the total memory size of the ruby system and verify it is equal 174 # to physmem. However, if Ruby memory is using sparse memory in SE 175 # mode, then the system should not back-up the memory state with 176 # the Memory Vector and thus the memory size bytes should stay at 0. 177 # Also set the numa bits to the appropriate values. 178 total_mem_size = MemorySize('0B') 179 180 ruby.block_size_bytes = options.cacheline_size 181 block_size_bits = int(math.log(options.cacheline_size, 2)) 182 183 if options.numa_high_bit: 184 numa_bit = options.numa_high_bit 185 else: 186 # if the numa_bit is not specified, set the directory bits as the 187 # lowest bits above the block offset bits, and the numa_bit as the 188 # highest of those directory bits 189 dir_bits = int(math.log(options.num_dirs, 2)) 190 numa_bit = block_size_bits + dir_bits - 1 191 192 for dir_cntrl in dir_cntrls: 193 total_mem_size.value += dir_cntrl.directory.size.value 194 dir_cntrl.directory.numa_high_bit = numa_bit 195 196 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 197 assert(total_mem_size.value == phys_mem_size) 198 ruby.mem_size = total_mem_size 199 200 # Connect the cpu sequencers and the piobus 201 if piobus != None: 202 for cpu_seq in cpu_sequencers: 203 cpu_seq.pio_master_port = piobus.slave 204 cpu_seq.mem_master_port = piobus.slave 205 206 if buildEnv['TARGET_ISA'] == "x86": 207 cpu_seq.pio_slave_port = piobus.master 208 209 ruby._cpu_ports = cpu_sequencers 210 ruby.num_of_sequencers = len(cpu_sequencers) 211 ruby.random_seed = options.random_seed
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