1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 91 unchanged lines hidden (view full) --- 100 sys_port_proxy = RubyPortProxy(version = 0, 101 physMemPort = system.physmem.port, 102 physmem = system.physmem, 103 ruby_system = ruby) 104 # Give the system port proxy a SimObject parent without creating a 105 # full-fledged controller 106 system.sys_port_proxy = sys_port_proxy 107 |
108 # Connect the system port for loading of binaries etc 109 system.system_port = system.sys_port_proxy.port 110 111 |
112 # 113 # Set the network classes based on the command line options 114 # 115 if options.garnet_network == "fixed": 116 class NetworkClass(GarnetNetwork_d): pass 117 class IntLinkClass(GarnetIntLink_d): pass 118 class ExtLinkClass(GarnetExtLink_d): pass 119 class RouterClass(GarnetRouter_d): pass --- 61 unchanged lines hidden (view full) --- 181 assert(total_mem_size.value == physmem_size) 182 183 ruby_profiler = RubyProfiler(ruby_system = ruby, 184 num_of_sequencers = len(cpu_sequencers)) 185 ruby.network = network 186 ruby.profiler = ruby_profiler 187 ruby.mem_size = total_mem_size 188 ruby._cpu_ruby_ports = cpu_sequencers |
189 ruby.random_seed = options.random_seed |