1# Copyright (c) 2012, 2017-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 77 unchanged lines hidden (view full) --- 86def setup_memory_controllers(system, ruby, dir_cntrls, options): 87 ruby.block_size_bytes = options.cacheline_size 88 ruby.memory_size_bits = 48 89 90 index = 0 91 mem_ctrls = [] 92 crossbars = [] 93 |
94 if options.numa_high_bit: 95 dir_bits = int(math.log(options.num_dirs, 2)) 96 intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1) 97 else: 98 # if the numa_bit is not specified, set the directory bits as the 99 # lowest bits above the block offset bits 100 intlv_size = options.cacheline_size 101 |
102 # Sets bits to be used for interleaving. Creates memory controllers 103 # attached to a directory controller. A separate controller is created 104 # for each address range as the abstract memory can handle only one 105 # contiguous address range as of now. 106 for dir_cntrl in dir_cntrls: 107 crossbar = None 108 if len(system.mem_ranges) > 1: 109 crossbar = IOXBar() 110 crossbars.append(crossbar) 111 dir_cntrl.memory = crossbar.slave 112 |
113 dir_ranges = [] |
114 for r in system.mem_ranges: 115 mem_ctrl = MemConfig.create_mem_ctrl( 116 MemConfig.get(options.mem_type), r, index, options.num_dirs, |
117 int(math.log(options.num_dirs, 2)), intlv_size) |
118 119 if options.access_backing_store: 120 mem_ctrl.kvm_map=False 121 122 mem_ctrls.append(mem_ctrl) |
123 dir_ranges.append(mem_ctrl.range) |
124 125 if crossbar != None: 126 mem_ctrl.port = crossbar.master 127 else: 128 mem_ctrl.port = dir_cntrl.memory 129 130 index += 1 |
131 dir_cntrl.addr_ranges = dir_ranges |
132 133 system.mem_ctrls = mem_ctrls 134 135 if len(crossbars) > 0: 136 ruby.crossbars = crossbars 137 138 139def create_topology(controllers, options): --- 65 unchanged lines hidden (view full) --- 205 ruby.num_of_sequencers = len(cpu_sequencers) 206 207 # Create a backing copy of physical memory in case required 208 if options.access_backing_store: 209 ruby.access_backing_store = True 210 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 211 in_addr_map=False) 212 |
213def create_directories(options, bootmem, ruby_system, system): |
214 dir_cntrl_nodes = [] |
215 for i in xrange(options.num_dirs): |
216 dir_cntrl = Directory_Controller() 217 dir_cntrl.version = i 218 dir_cntrl.directory = RubyDirectoryMemory() 219 dir_cntrl.ruby_system = ruby_system |
220 221 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 222 dir_cntrl_nodes.append(dir_cntrl) 223 224 if bootmem is not None: 225 rom_dir_cntrl = Directory_Controller() 226 rom_dir_cntrl.directory = RubyDirectoryMemory() 227 rom_dir_cntrl.ruby_system = ruby_system --- 16 unchanged lines hidden --- |