1# Copyright (c) 2012, 2017-2018 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 120 unchanged lines hidden (view full) --- 130 Must return an object which is a subclass of BaseTopology 131 found in configs/topologies/BaseTopology.py 132 This is a wrapper for the legacy topologies. 133 """ 134 exec "import topologies.%s as Topo" % options.topology 135 topology = eval("Topo.%s(controllers)" % options.topology) 136 return topology 137 |
138def create_system(options, full_system, system, piobus = None, dma_ports = [], 139 bootmem=None): |
140 141 system.ruby = RubySystem() 142 ruby = system.ruby 143 144 # Create the network object 145 (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 146 Network.create_network(options, ruby) 147 ruby.network = network 148 149 protocol = buildEnv['PROTOCOL'] 150 exec "import %s" % protocol 151 try: 152 (cpu_sequencers, dir_cntrls, topology) = \ 153 eval("%s.create_system(options, full_system, system, dma_ports,\ |
154 bootmem, ruby)" |
155 % protocol) 156 except: 157 print("Error: could not create sytem for ruby protocol %s" % protocol) 158 raise 159 160 # Create the network topology 161 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 162 RouterClass) --- 31 unchanged lines hidden (view full) --- 194 ruby.num_of_sequencers = len(cpu_sequencers) 195 196 # Create a backing copy of physical memory in case required 197 if options.access_backing_store: 198 ruby.access_backing_store = True 199 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 200 in_addr_map=False) 201 |
202def create_directories(options, mem_ranges, bootmem, ruby_system, 203 system): |
204 dir_cntrl_nodes = [] 205 if options.numa_high_bit: 206 numa_bit = options.numa_high_bit 207 else: 208 # if the numa_bit is not specified, set the directory bits as the 209 # lowest bits above the block offset bits, and the numa_bit as the 210 # highest of those directory bits 211 dir_bits = int(math.log(options.num_dirs, 2)) --- 12 unchanged lines hidden (view full) --- 224 dir_cntrl = Directory_Controller() 225 dir_cntrl.version = i 226 dir_cntrl.directory = RubyDirectoryMemory() 227 dir_cntrl.ruby_system = ruby_system 228 dir_cntrl.addr_ranges = dir_ranges 229 230 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 231 dir_cntrl_nodes.append(dir_cntrl) |
232 |
233 if bootmem is not None: 234 rom_dir_cntrl = Directory_Controller() 235 rom_dir_cntrl.directory = RubyDirectoryMemory() 236 rom_dir_cntrl.ruby_system = ruby_system 237 rom_dir_cntrl.version = i + 1 238 rom_dir_cntrl.memory = bootmem.port 239 rom_dir_cntrl.addr_ranges = bootmem.range 240 return (dir_cntrl_nodes, rom_dir_cntrl) 241 242 return (dir_cntrl_nodes, None) 243 |
244def send_evicts(options): 245 # currently, 2 scenarios warrant forwarding evictions to the CPU: 246 # 1. The O3 model must keep the LSQ coherent with the caches 247 # 2. The x86 mwait instruction is built on top of coherence invalidations 248 # 3. The local exclusive monitor in ARM systems 249 if options.cpu_type == "DerivO3CPU" or \ 250 buildEnv['TARGET_ISA'] in ('x86', 'arm'): 251 return True 252 return False |