1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 68 unchanged lines hidden (view full) --- 77 # ruby mapping options 78 parser.add_option("--numa-high-bit", type="int", default=0, 79 help="high order address bit to use for numa mapping. " \ 80 "0 = highest bit, not specified = lowest bit") 81 82 parser.add_option("--recycle-latency", type="int", default=10, 83 help="Recycle latency for ruby controller input buffers") 84 |
85 protocol = buildEnv['PROTOCOL'] 86 exec "import %s" % protocol 87 eval("%s.define_options(parser)" % protocol) 88 89def setup_memory_controllers(system, ruby, dir_cntrls, options): 90 ruby.block_size_bytes = options.cacheline_size 91 ruby.memory_size_bits = 48 92 block_size_bits = int(math.log(options.cacheline_size, 2)) --- 135 unchanged lines hidden (view full) --- 228 cpu_seq.pio_master_port = piobus.slave 229 cpu_seq.mem_master_port = piobus.slave 230 231 if buildEnv['TARGET_ISA'] == "x86": 232 cpu_seq.pio_slave_port = piobus.master 233 234 ruby._cpu_ports = cpu_sequencers 235 ruby.num_of_sequencers = len(cpu_sequencers) |
236 237 # Create a backing copy of physical memory in case required 238 if options.access_backing_store: 239 ruby.access_backing_store = True 240 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 241 in_addr_map=False) 242 243def send_evicts(options): 244 # currently, 2 scenarios warrant forwarding evictions to the CPU: 245 # 1. The O3 model must keep the LSQ coherent with the caches 246 # 2. The x86 mwait instruction is built on top of coherence invalidations 247 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 248 return True 249 return False |