1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 93 unchanged lines hidden (view full) --- 102 103 system.ruby = RubySystem(no_mem_vec = options.use_map) 104 ruby = system.ruby 105 106 protocol = buildEnv['PROTOCOL'] 107 exec "import %s" % protocol 108 try: 109 (cpu_sequencers, dir_cntrls, topology) = \ |
110 eval("%s.create_system(options, system, dma_ports, ruby)" |
111 % protocol) 112 except: 113 print "Error: could not create sytem for ruby protocol %s" % protocol 114 raise 115 116 # Create a port proxy for connecting the system port. This is 117 # independent of the protocol and kept in the protocol-agnostic 118 # part (i.e. here). --- 63 unchanged lines hidden (view full) --- 182 total_mem_size.value += dir_cntrl.directory.size.value 183 dir_cntrl.directory.numa_high_bit = numa_bit 184 185 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 186 assert(total_mem_size.value == phys_mem_size) 187 188 ruby.network = network 189 ruby.mem_size = total_mem_size |
190 191 # Connect the cpu sequencers and the piobus 192 if piobus != None: 193 for cpu_seq in cpu_sequencers: 194 cpu_seq.pio_master_port = piobus.slave 195 cpu_seq.mem_master_port = piobus.slave 196 197 if buildEnv['TARGET_ISA'] == "x86": 198 cpu_seq.pio_slave_port = piobus.master 199 |
200 ruby._cpu_ruby_ports = cpu_sequencers 201 ruby.num_of_sequencers = len(cpu_sequencers) 202 ruby.random_seed = options.random_seed |