1# Copyright (c) 2012 ARM Limited
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
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39#
40# Authors: Brad Beckmann
41
42import math
43import m5
44from m5.objects import *
45from m5.defines import buildEnv
46from m5.util import addToPath, fatal
47
48import MemConfig
49addToPath('../topologies')
50
51def define_options(parser):
52 # By default, ruby uses the simple timing cpu
53 parser.set_defaults(cpu_type="timing")
54
55 parser.add_option("--ruby-clock", action="store", type="string",
56 default='2GHz',
57 help="Clock for blocks running at Ruby system's speed")
58
59 # Options related to cache structure
60 parser.add_option("--ports", action="store", type="int", default=4,
61 help="used of transitions per cycle which is a proxy \
62 for the number of ports.")
63
64 # ruby network options
65 parser.add_option("--topology", type="string", default="Crossbar",
66 help="check src/mem/ruby/network/topologies for complete set")
67 parser.add_option("--mesh-rows", type="int", default=1,
68 help="the number of rows in the mesh topology")
69 parser.add_option("--garnet-network", type="choice",
70 choices=['fixed', 'flexible'], help="'fixed'|'flexible'")
71 parser.add_option("--network-fault-model", action="store_true", default=False,
72 help="enable network fault model: see src/mem/ruby/network/fault_model/")
73
74 # ruby mapping options
75 parser.add_option("--numa-high-bit", type="int", default=0,
76 help="high order address bit to use for numa mapping. " \
77 "0 = highest bit, not specified = lowest bit")
78
79 parser.add_option("--recycle-latency", type="int", default=10,
80 help="Recycle latency for ruby controller input buffers")
81
82 parser.add_option("--random_seed", type="int", default=1234,
83 help="Used for seeding the random number generator")
84
85 protocol = buildEnv['PROTOCOL']
86 exec "import %s" % protocol
87 eval("%s.define_options(parser)" % protocol)
88
89def setup_memory_controllers(system, ruby, dir_cntrls, options):
90 ruby.block_size_bytes = options.cacheline_size
91 ruby.memory_size_bits = 48
92 block_size_bits = int(math.log(options.cacheline_size, 2))
93
94 if options.numa_high_bit:
95 numa_bit = options.numa_high_bit
96 else:
97 # if the numa_bit is not specified, set the directory bits as the
98 # lowest bits above the block offset bits, and the numa_bit as the
99 # highest of those directory bits
100 dir_bits = int(math.log(options.num_dirs, 2))
101 numa_bit = block_size_bits + dir_bits - 1
102
103 index = 0
104 mem_ctrls = []
105 crossbars = []
106
107 # Sets bits to be used for interleaving. Creates memory controllers
108 # attached to a directory controller. A separate controller is created
109 # for each address range as the abstract memory can handle only one
110 # contiguous address range as of now.
111 for dir_cntrl in dir_cntrls:
112 dir_cntrl.directory.numa_high_bit = numa_bit
113
114 crossbar = None
115 if len(system.mem_ranges) > 1:
116 crossbar = NoncoherentXBar()
117 crossbars.append(crossbar)
118 dir_cntrl.memory = crossbar.slave
119
120 for r in system.mem_ranges:
121 mem_ctrl = MemConfig.create_mem_ctrl(
122 MemConfig.get(options.mem_type), r, index, options.num_dirs,
123 int(math.log(options.num_dirs, 2)), options.cacheline_size)
124
125 mem_ctrls.append(mem_ctrl)
126
127 if crossbar != None:
128 mem_ctrl.port = crossbar.master
129 else:
130 mem_ctrl.port = dir_cntrl.memory
131
132 index += 1
133
134 system.mem_ctrls = mem_ctrls
135
136 if len(crossbars) > 0:
137 ruby.crossbars = crossbars
138
139
140def create_topology(controllers, options):
141 """ Called from create_system in configs/ruby/<protocol>.py
142 Must return an object which is a subclass of BaseTopology
143 found in configs/topologies/BaseTopology.py
144 This is a wrapper for the legacy topologies.
145 """
146 exec "import %s as Topo" % options.topology
147 topology = eval("Topo.%s(controllers)" % options.topology)
148 return topology
149
150def create_system(options, full_system, system, piobus = None, dma_ports = []):
151
152 system.ruby = RubySystem()
153 ruby = system.ruby
154
155 # Set the network classes based on the command line options
156 if options.garnet_network == "fixed":
157 NetworkClass = GarnetNetwork_d
158 IntLinkClass = GarnetIntLink_d
159 ExtLinkClass = GarnetExtLink_d
160 RouterClass = GarnetRouter_d
161 InterfaceClass = GarnetNetworkInterface_d
162
163 elif options.garnet_network == "flexible":
164 NetworkClass = GarnetNetwork
165 IntLinkClass = GarnetIntLink
166 ExtLinkClass = GarnetExtLink
167 RouterClass = GarnetRouter
168 InterfaceClass = GarnetNetworkInterface
169
170 else:
171 NetworkClass = SimpleNetwork
172 IntLinkClass = SimpleIntLink
173 ExtLinkClass = SimpleExtLink
174 RouterClass = Switch
175 InterfaceClass = None
176
177 # Instantiate the network object so that the controllers can connect to it.
178 network = NetworkClass(ruby_system = ruby, topology = options.topology,
179 routers = [], ext_links = [], int_links = [], netifs = [])
180 ruby.network = network
181
182 protocol = buildEnv['PROTOCOL']
183 exec "import %s" % protocol
184 try:
185 (cpu_sequencers, dir_cntrls, topology) = \
186 eval("%s.create_system(options, full_system, system, dma_ports,\
187 ruby)"
188 % protocol)
189 except:
190 print "Error: could not create sytem for ruby protocol %s" % protocol
191 raise
192
193 # Create a port proxy for connecting the system port. This is
194 # independent of the protocol and kept in the protocol-agnostic
195 # part (i.e. here).
196 sys_port_proxy = RubyPortProxy(ruby_system = ruby)
197
198 # Give the system port proxy a SimObject parent without creating a
199 # full-fledged controller
200 system.sys_port_proxy = sys_port_proxy
201
202 # Connect the system port for loading of binaries etc
203 system.system_port = system.sys_port_proxy.slave
204
205 # Create the network topology
206 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
207 RouterClass)
208
209 if InterfaceClass != None:
210 netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)]
211 network.netifs = netifs
212
213 if options.network_fault_model:
214 assert(options.garnet_network == "fixed")
215 network.enable_fault_model = True
216 network.fault_model = FaultModel()
217
218 setup_memory_controllers(system, ruby, dir_cntrls, options)
219
220 # Connect the cpu sequencers and the piobus
221 if piobus != None:
222 for cpu_seq in cpu_sequencers:
223 cpu_seq.pio_master_port = piobus.slave
224 cpu_seq.mem_master_port = piobus.slave
225
226 if buildEnv['TARGET_ISA'] == "x86":
227 cpu_seq.pio_slave_port = piobus.master
228
229 ruby._cpu_ports = cpu_sequencers
230 ruby.num_of_sequencers = len(cpu_sequencers)
231 ruby.random_seed = options.random_seed