1# Copyright (c) 2012, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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130 Must return an object which is a subclass of BaseTopology
131 found in configs/topologies/BaseTopology.py
132 This is a wrapper for the legacy topologies.
133 """
134 exec "import topologies.%s as Topo" % options.topology
135 topology = eval("Topo.%s(controllers)" % options.topology)
136 return topology
137
138def create_system(options, full_system, system, piobus = None, dma_ports = []):
139
140 system.ruby = RubySystem()
141 ruby = system.ruby
142
143 # Create the network object
144 (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
145 Network.create_network(options, ruby)
146 ruby.network = network
147
148 protocol = buildEnv['PROTOCOL']
149 exec "import %s" % protocol
150 try:
151 (cpu_sequencers, dir_cntrls, topology) = \
152 eval("%s.create_system(options, full_system, system, dma_ports,\
153 ruby)"
154 % protocol)
155 except:
156 print("Error: could not create sytem for ruby protocol %s" % protocol)
157 raise
158
159 # Create the network topology
160 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
161 RouterClass)

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193 ruby.num_of_sequencers = len(cpu_sequencers)
194
195 # Create a backing copy of physical memory in case required
196 if options.access_backing_store:
197 ruby.access_backing_store = True
198 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
199 in_addr_map=False)
200
201def create_directories(options, mem_ranges, ruby_system):
202 dir_cntrl_nodes = []
203 if options.numa_high_bit:
204 numa_bit = options.numa_high_bit
205 else:
206 # if the numa_bit is not specified, set the directory bits as the
207 # lowest bits above the block offset bits, and the numa_bit as the
208 # highest of those directory bits
209 dir_bits = int(math.log(options.num_dirs, 2))

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222 dir_cntrl = Directory_Controller()
223 dir_cntrl.version = i
224 dir_cntrl.directory = RubyDirectoryMemory()
225 dir_cntrl.ruby_system = ruby_system
226 dir_cntrl.addr_ranges = dir_ranges
227
228 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
229 dir_cntrl_nodes.append(dir_cntrl)
230 return dir_cntrl_nodes
231
232def send_evicts(options):
233 # currently, 2 scenarios warrant forwarding evictions to the CPU:
234 # 1. The O3 model must keep the LSQ coherent with the caches
235 # 2. The x86 mwait instruction is built on top of coherence invalidations
236 # 3. The local exclusive monitor in ARM systems
237 if options.cpu_type == "DerivO3CPU" or \
238 buildEnv['TARGET_ISA'] in ('x86', 'arm'):
239 return True
240 return False