1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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79 protocol = buildEnv['PROTOCOL']
80 exec "import %s" % protocol
81 eval("%s.define_options(parser)" % protocol)
82 Network.define_options(parser)
83
84def setup_memory_controllers(system, ruby, dir_cntrls, options):
85 ruby.block_size_bytes = options.cacheline_size
86 ruby.memory_size_bits = 48
87 block_size_bits = int(math.log(options.cacheline_size, 2))
88
89 if options.numa_high_bit:
90 numa_bit = options.numa_high_bit
91 else:
92 # if the numa_bit is not specified, set the directory bits as the
93 # lowest bits above the block offset bits, and the numa_bit as the
94 # highest of those directory bits
95 dir_bits = int(math.log(options.num_dirs, 2))
96 numa_bit = block_size_bits + dir_bits - 1
97
98 index = 0
99 mem_ctrls = []
100 crossbars = []
101
102 # Sets bits to be used for interleaving. Creates memory controllers
103 # attached to a directory controller. A separate controller is created
104 # for each address range as the abstract memory can handle only one
105 # contiguous address range as of now.
106 for dir_cntrl in dir_cntrls:
107 dir_cntrl.directory.numa_high_bit = numa_bit
108
109 crossbar = None
110 if len(system.mem_ranges) > 1:
111 crossbar = IOXBar()
112 crossbars.append(crossbar)
113 dir_cntrl.memory = crossbar.slave
114
115 for r in system.mem_ranges:
116 mem_ctrl = MemConfig.create_mem_ctrl(

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203 ruby.num_of_sequencers = len(cpu_sequencers)
204
205 # Create a backing copy of physical memory in case required
206 if options.access_backing_store:
207 ruby.access_backing_store = True
208 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
209 in_addr_map=False)
210
211def send_evicts(options):
212 # currently, 2 scenarios warrant forwarding evictions to the CPU:
213 # 1. The O3 model must keep the LSQ coherent with the caches
214 # 2. The x86 mwait instruction is built on top of coherence invalidations
215 if options.cpu_type == "DerivO3CPU" or buildEnv['TARGET_ISA'] == 'x86':
216 return True
217 return False