1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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226 if piobus != None:
227 for cpu_seq in cpu_sequencers:
228 cpu_seq.pio_master_port = piobus.slave
229 cpu_seq.mem_master_port = piobus.slave
230
231 if buildEnv['TARGET_ISA'] == "x86":
232 cpu_seq.pio_slave_port = piobus.master
233
234 ruby._cpu_ports = cpu_sequencers
235 ruby.num_of_sequencers = len(cpu_sequencers)
236
237 # Create a backing copy of physical memory in case required
238 if options.access_backing_store:
239 ruby.access_backing_store = True
240 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
241 in_addr_map=False)
242
243def send_evicts(options):
244 # currently, 2 scenarios warrant forwarding evictions to the CPU:
245 # 1. The O3 model must keep the LSQ coherent with the caches
246 # 2. The x86 mwait instruction is built on top of coherence invalidations
247 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86':
248 return True
249 return False