1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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51def define_options(parser):
52 # By default, ruby uses the simple timing cpu
53 parser.set_defaults(cpu_type="timing")
54
55 parser.add_option("--ruby-clock", action="store", type="string",
56 default='2GHz',
57 help="Clock for blocks running at Ruby system's speed")
58
59 # Options related to cache structure
60 parser.add_option("--ports", action="store", type="int", default=4,
61 help="used of transitions per cycle which is a proxy \
62 for the number of ports.")
63
64 # ruby network options
65 parser.add_option("--topology", type="string", default="Crossbar",
66 help="check src/mem/ruby/network/topologies for complete set")

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224 cpu_seq.mem_master_port = piobus.slave
225
226 if buildEnv['TARGET_ISA'] == "x86":
227 cpu_seq.pio_slave_port = piobus.master
228
229 ruby._cpu_ports = cpu_sequencers
230 ruby.num_of_sequencers = len(cpu_sequencers)
231 ruby.random_seed = options.random_seed