1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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40# Authors: Brad Beckmann
41
42import math
43import m5
44from m5.objects import *
45from m5.defines import buildEnv
46from m5.util import addToPath, fatal
47
48addToPath('../topologies')
49
50def define_options(parser):
51 # By default, ruby uses the simple timing cpu
52 parser.set_defaults(cpu_type="timing")
53
54 parser.add_option("--ruby-clock", action="store", type="string",
55 default='2GHz',

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70 parser.add_option("--network-fault-model", action="store_true", default=False,
71 help="enable network fault model: see src/mem/ruby/network/fault_model/")
72
73 # ruby mapping options
74 parser.add_option("--numa-high-bit", type="int", default=0,
75 help="high order address bit to use for numa mapping. " \
76 "0 = highest bit, not specified = lowest bit")
77
78 # ruby sparse memory options
79 parser.add_option("--use-map", action="store_true", default=False)
80 parser.add_option("--map-levels", type="int", default=4)
81
82 parser.add_option("--recycle-latency", type="int", default=10,
83 help="Recycle latency for ruby controller input buffers")
84
85 parser.add_option("--random_seed", type="int", default=1234,
86 help="Used for seeding the random number generator")
87
88 parser.add_option("--ruby_stats", type="string", default="ruby.stats")
89
90 protocol = buildEnv['PROTOCOL']
91 exec "import %s" % protocol
92 eval("%s.define_options(parser)" % protocol)
93
94def create_topology(controllers, options):
95 """ Called from create_system in configs/ruby/<protocol>.py
96 Must return an object which is a subclass of BaseTopology
97 found in configs/topologies/BaseTopology.py
98 This is a wrapper for the legacy topologies.
99 """
100 exec "import %s as Topo" % options.topology
101 topology = eval("Topo.%s(controllers)" % options.topology)
102 return topology
103
104def create_system(options, full_system, system, piobus = None, dma_ports = []):
105
106 system.ruby = RubySystem(no_mem_vec = options.use_map)
107 ruby = system.ruby
108
109 # Set the network classes based on the command line options
110 if options.garnet_network == "fixed":
111 NetworkClass = GarnetNetwork_d
112 IntLinkClass = GarnetIntLink_d
113 ExtLinkClass = GarnetExtLink_d
114 RouterClass = GarnetRouter_d

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164 netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)]
165 network.netifs = netifs
166
167 if options.network_fault_model:
168 assert(options.garnet_network == "fixed")
169 network.enable_fault_model = True
170 network.fault_model = FaultModel()
171
172 # Loop through the directory controlers.
173 # Determine the total memory size of the ruby system and verify it is equal
174 # to physmem. However, if Ruby memory is using sparse memory in SE
175 # mode, then the system should not back-up the memory state with
176 # the Memory Vector and thus the memory size bytes should stay at 0.
177 # Also set the numa bits to the appropriate values.
178 total_mem_size = MemorySize('0B')
179
180 ruby.block_size_bytes = options.cacheline_size
181 block_size_bits = int(math.log(options.cacheline_size, 2))
182
183 if options.numa_high_bit:
184 numa_bit = options.numa_high_bit
185 else:
186 # if the numa_bit is not specified, set the directory bits as the
187 # lowest bits above the block offset bits, and the numa_bit as the
188 # highest of those directory bits
189 dir_bits = int(math.log(options.num_dirs, 2))
190 numa_bit = block_size_bits + dir_bits - 1
191
192 for dir_cntrl in dir_cntrls:
193 total_mem_size.value += dir_cntrl.directory.size.value
194 dir_cntrl.directory.numa_high_bit = numa_bit
195
196 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
197 assert(total_mem_size.value == phys_mem_size)
198 ruby.mem_size = total_mem_size
199
200 # Connect the cpu sequencers and the piobus
201 if piobus != None:
202 for cpu_seq in cpu_sequencers:
203 cpu_seq.pio_master_port = piobus.slave
204 cpu_seq.mem_master_port = piobus.slave
205
206 if buildEnv['TARGET_ISA'] == "x86":
207 cpu_seq.pio_slave_port = piobus.master
208
209 ruby._cpu_ports = cpu_sequencers
210 ruby.num_of_sequencers = len(cpu_sequencers)
211 ruby.random_seed = options.random_seed