MOESI_hammer.py (9841:69c158420c51) | MOESI_hammer.py (10006:8fa94dcfd545) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 67 unchanged lines hidden (view full) --- 76 dma_cntrl_nodes = [] 77 78 # 79 # Must create the individual controllers before the network to ensure the 80 # controller constructors are called before the network constructor 81 # 82 block_size_bits = int(math.log(options.cacheline_size, 2)) 83 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 67 unchanged lines hidden (view full) --- 76 dma_cntrl_nodes = [] 77 78 # 79 # Must create the individual controllers before the network to ensure the 80 # controller constructors are called before the network constructor 81 # 82 block_size_bits = int(math.log(options.cacheline_size, 2)) 83 |
84 cntrl_count = 0 85 | |
86 for i in xrange(options.num_cpus): 87 # 88 # First create the Ruby objects associated with this cpu 89 # 90 l1i_cache = L1Cache(size = options.l1i_size, 91 assoc = options.l1i_assoc, 92 start_index_bit = block_size_bits, 93 is_icache = True) 94 l1d_cache = L1Cache(size = options.l1d_size, 95 assoc = options.l1d_assoc, 96 start_index_bit = block_size_bits) 97 l2_cache = L2Cache(size = options.l2_size, 98 assoc = options.l2_assoc, 99 start_index_bit = block_size_bits) 100 101 l1_cntrl = L1Cache_Controller(version = i, | 84 for i in xrange(options.num_cpus): 85 # 86 # First create the Ruby objects associated with this cpu 87 # 88 l1i_cache = L1Cache(size = options.l1i_size, 89 assoc = options.l1i_assoc, 90 start_index_bit = block_size_bits, 91 is_icache = True) 92 l1d_cache = L1Cache(size = options.l1d_size, 93 assoc = options.l1d_assoc, 94 start_index_bit = block_size_bits) 95 l2_cache = L2Cache(size = options.l2_size, 96 assoc = options.l2_assoc, 97 start_index_bit = block_size_bits) 98 99 l1_cntrl = L1Cache_Controller(version = i, |
102 cntrl_id = cntrl_count, | |
103 L1Icache = l1i_cache, 104 L1Dcache = l1d_cache, 105 L2cache = l2_cache, 106 no_mig_atomic = not \ 107 options.allow_atomic_migration, 108 send_evictions = ( 109 options.cpu_type == "detailed"), 110 transitions_per_cycle = options.ports, --- 14 unchanged lines hidden (view full) --- 125 126 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # 130 cpu_sequencers.append(cpu_seq) 131 l1_cntrl_nodes.append(l1_cntrl) 132 | 100 L1Icache = l1i_cache, 101 L1Dcache = l1d_cache, 102 L2cache = l2_cache, 103 no_mig_atomic = not \ 104 options.allow_atomic_migration, 105 send_evictions = ( 106 options.cpu_type == "detailed"), 107 transitions_per_cycle = options.ports, --- 14 unchanged lines hidden (view full) --- 122 123 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 124 # 125 # Add controllers and sequencers to the appropriate lists 126 # 127 cpu_sequencers.append(cpu_seq) 128 l1_cntrl_nodes.append(l1_cntrl) 129 |
133 cntrl_count += 1 134 | |
135 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 136 assert(phys_mem_size % options.num_dirs == 0) 137 mem_module_size = phys_mem_size / options.num_dirs 138 139 # 140 # determine size and index bits for probe filter 141 # By default, the probe filter size is configured to be twice the 142 # size of the L2 cache. --- 35 unchanged lines hidden (view full) --- 178 179 dir_size = MemorySize('0B') 180 dir_size.value = mem_module_size 181 182 pf = ProbeFilter(size = pf_size, assoc = 4, 183 start_index_bit = pf_start_bit) 184 185 dir_cntrl = Directory_Controller(version = i, | 130 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 131 assert(phys_mem_size % options.num_dirs == 0) 132 mem_module_size = phys_mem_size / options.num_dirs 133 134 # 135 # determine size and index bits for probe filter 136 # By default, the probe filter size is configured to be twice the 137 # size of the L2 cache. --- 35 unchanged lines hidden (view full) --- 173 174 dir_size = MemorySize('0B') 175 dir_size.value = mem_module_size 176 177 pf = ProbeFilter(size = pf_size, assoc = 4, 178 start_index_bit = pf_start_bit) 179 180 dir_cntrl = Directory_Controller(version = i, |
186 cntrl_id = cntrl_count, | |
187 directory = \ 188 RubyDirectoryMemory( \ 189 version = i, 190 size = dir_size, 191 use_map = options.use_map, 192 map_levels = \ 193 options.map_levels, 194 numa_high_bit = \ --- 6 unchanged lines hidden (view full) --- 201 ruby_system = ruby_system) 202 203 if options.recycle_latency: 204 dir_cntrl.recycle_latency = options.recycle_latency 205 206 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 207 dir_cntrl_nodes.append(dir_cntrl) 208 | 181 directory = \ 182 RubyDirectoryMemory( \ 183 version = i, 184 size = dir_size, 185 use_map = options.use_map, 186 map_levels = \ 187 options.map_levels, 188 numa_high_bit = \ --- 6 unchanged lines hidden (view full) --- 195 ruby_system = ruby_system) 196 197 if options.recycle_latency: 198 dir_cntrl.recycle_latency = options.recycle_latency 199 200 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 201 dir_cntrl_nodes.append(dir_cntrl) 202 |
209 cntrl_count += 1 210 | |
211 for i, dma_port in enumerate(dma_ports): 212 # 213 # Create the Ruby objects associated with the dma controller 214 # 215 dma_seq = DMASequencer(version = i, 216 ruby_system = ruby_system) 217 218 dma_cntrl = DMA_Controller(version = i, | 203 for i, dma_port in enumerate(dma_ports): 204 # 205 # Create the Ruby objects associated with the dma controller 206 # 207 dma_seq = DMASequencer(version = i, 208 ruby_system = ruby_system) 209 210 dma_cntrl = DMA_Controller(version = i, |
219 cntrl_id = cntrl_count, | |
220 dma_sequencer = dma_seq, 221 transitions_per_cycle = options.ports, 222 ruby_system = ruby_system) 223 224 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 225 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 226 dma_cntrl_nodes.append(dma_cntrl) 227 228 if options.recycle_latency: 229 dma_cntrl.recycle_latency = options.recycle_latency 230 | 211 dma_sequencer = dma_seq, 212 transitions_per_cycle = options.ports, 213 ruby_system = ruby_system) 214 215 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 216 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 217 dma_cntrl_nodes.append(dma_cntrl) 218 219 if options.recycle_latency: 220 dma_cntrl.recycle_latency = options.recycle_latency 221 |
231 cntrl_count += 1 232 | |
233 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes | 222 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes |
234 | |
235 topology = create_topology(all_cntrls, options) 236 237 return (cpu_sequencers, dir_cntrl_nodes, topology) | 223 topology = create_topology(all_cntrls, options) 224 225 return (cpu_sequencers, dir_cntrl_nodes, topology) |