Cross Reference: /gem5/configs/ruby/MOESI

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MOESI_hammer.py (9318:dec0b284ded9)	MOESI_hammer.py (9468:721718c62859)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 108 unchanged lines hidden (view full) --- 117 l1_cntrl.sequencer = cpu_seq 118 119 if piobus != None: 120 cpu_seq.pio_port = piobus.slave 121 122 if options.recycle_latency: 123 l1_cntrl.recycle_latency = options.recycle_latency 124	1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 108 unchanged lines hidden (view full) --- 117 l1_cntrl.sequencer = cpu_seq 118 119 if piobus != None: 120 cpu_seq.pio_port = piobus.slave 121 122 if options.recycle_latency: 123 l1_cntrl.recycle_latency = options.recycle_latency 124
125 exec("system.l1_cntrl%d = l1_cntrl" % i)	125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
126 # 127 # Add controllers and sequencers to the appropriate lists 128 # 129 cpu_sequencers.append(cpu_seq) 130 l1_cntrl_nodes.append(l1_cntrl) 131 132 cntrl_count += 1 133 --- 53 unchanged lines hidden (view full) --- 187 memBuffer = mem_cntrl, 188 probe_filter_enabled = options.pf_on, 189 full_bit_dir_enabled = options.dir_on, 190 ruby_system = ruby_system) 191 192 if options.recycle_latency: 193 dir_cntrl.recycle_latency = options.recycle_latency 194	126 # 127 # Add controllers and sequencers to the appropriate lists 128 # 129 cpu_sequencers.append(cpu_seq) 130 l1_cntrl_nodes.append(l1_cntrl) 131 132 cntrl_count += 1 133 --- 53 unchanged lines hidden (view full) --- 187 memBuffer = mem_cntrl, 188 probe_filter_enabled = options.pf_on, 189 full_bit_dir_enabled = options.dir_on, 190 ruby_system = ruby_system) 191 192 if options.recycle_latency: 193 dir_cntrl.recycle_latency = options.recycle_latency 194
195 exec("system.dir_cntrl%d = dir_cntrl" % i)	195 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
196 dir_cntrl_nodes.append(dir_cntrl) 197 198 cntrl_count += 1 199 200 for i, dma_port in enumerate(dma_ports): 201 # 202 # Create the Ruby objects associated with the dma controller 203 # 204 dma_seq = DMASequencer(version = i, 205 ruby_system = ruby_system) 206 207 dma_cntrl = DMA_Controller(version = i, 208 cntrl_id = cntrl_count, 209 dma_sequencer = dma_seq, 210 ruby_system = ruby_system) 211	196 dir_cntrl_nodes.append(dir_cntrl) 197 198 cntrl_count += 1 199 200 for i, dma_port in enumerate(dma_ports): 201 # 202 # Create the Ruby objects associated with the dma controller 203 # 204 dma_seq = DMASequencer(version = i, 205 ruby_system = ruby_system) 206 207 dma_cntrl = DMA_Controller(version = i, 208 cntrl_id = cntrl_count, 209 dma_sequencer = dma_seq, 210 ruby_system = ruby_system) 211
212 exec("system.dma_cntrl%d = dma_cntrl" % i) 213 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)	212 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 213 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
214 dma_cntrl_nodes.append(dma_cntrl) 215 216 if options.recycle_latency: 217 dma_cntrl.recycle_latency = options.recycle_latency 218 219 cntrl_count += 1 220 221 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 222 223 topology = create_topology(all_cntrls, options) 224 225 return (cpu_sequencers, dir_cntrl_nodes, topology)	214 dma_cntrl_nodes.append(dma_cntrl) 215 216 if options.recycle_latency: 217 dma_cntrl.recycle_latency = options.recycle_latency 218 219 cntrl_count += 1 220 221 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 222 223 topology = create_topology(all_cntrls, options) 224 225 return (cpu_sequencers, dir_cntrl_nodes, topology)