MOESI_hammer.py (8653:15d4da9d2042) MOESI_hammer.py (8717:5c253f1031d7)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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99
100 l1_cntrl = L1Cache_Controller(version = i,
101 cntrl_id = cntrl_count,
102 L1IcacheMemory = l1i_cache,
103 L1DcacheMemory = l1d_cache,
104 L2cacheMemory = l2_cache,
105 no_mig_atomic = not \
106 options.allow_atomic_migration,
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 90 unchanged lines hidden (view full) ---

99
100 l1_cntrl = L1Cache_Controller(version = i,
101 cntrl_id = cntrl_count,
102 L1IcacheMemory = l1i_cache,
103 L1DcacheMemory = l1d_cache,
104 L2cacheMemory = l2_cache,
105 no_mig_atomic = not \
106 options.allow_atomic_migration,
107 send_evictions = (
108 options.cpu_type == "detailed"),
107 ruby_system = ruby_system)
108
109 cpu_seq = RubySequencer(version = i,
110 icache = l1i_cache,
111 dcache = l1d_cache,
112 physMemPort = system.physmem.port,
113 physmem = system.physmem,
114 ruby_system = ruby_system)

--- 112 unchanged lines hidden ---
109 ruby_system = ruby_system)
110
111 cpu_seq = RubySequencer(version = i,
112 icache = l1i_cache,
113 dcache = l1d_cache,
114 physMemPort = system.physmem.port,
115 physmem = system.physmem,
116 ruby_system = ruby_system)

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