MOESI_hammer.py (8257:7226aebb77b4) MOESI_hammer.py (8322:19949c6de823)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 82 unchanged lines hidden (view full) ---

91 start_index_bit = block_size_bits)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 82 unchanged lines hidden (view full) ---

91 start_index_bit = block_size_bits)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
99 l1_cntrl = L1Cache_Controller(version = i,
100 cntrl_id = cntrl_count,
101 L1IcacheMemory = l1i_cache,
102 L1DcacheMemory = l1d_cache,
103 L2cacheMemory = l2_cache,
104 no_mig_atomic = not \
105 options.allow_atomic_migration)
106
99 cpu_seq = RubySequencer(version = i,
100 icache = l1i_cache,
101 dcache = l1d_cache,
102 physMemPort = system.physmem.port,
103 physmem = system.physmem)
104
107 cpu_seq = RubySequencer(version = i,
108 icache = l1i_cache,
109 dcache = l1d_cache,
110 physMemPort = system.physmem.port,
111 physmem = system.physmem)
112
113 l1_cntrl.sequencer = cpu_seq
114
105 if piobus != None:
106 cpu_seq.pio_port = piobus.port
107
115 if piobus != None:
116 cpu_seq.pio_port = piobus.port
117
108 l1_cntrl = L1Cache_Controller(version = i,
109 cntrl_id = cntrl_count,
110 sequencer = cpu_seq,
111 L1IcacheMemory = l1i_cache,
112 L1DcacheMemory = l1d_cache,
113 L2cacheMemory = l2_cache,
114 no_mig_atomic = not \
115 options.allow_atomic_migration)
116
117 if options.recycle_latency:
118 l1_cntrl.recycle_latency = options.recycle_latency
119
120 exec("system.l1_cntrl%d = l1_cntrl" % i)
121 #
122 # Add controllers and sequencers to the appropriate lists
123 #
124 cpu_sequencers.append(cpu_seq)

--- 95 unchanged lines hidden --- 		118 if options.recycle_latency:
119 l1_cntrl.recycle_latency = options.recycle_latency
120
121 exec("system.l1_cntrl%d = l1_cntrl" % i)
122 #
123 # Add controllers and sequencers to the appropriate lists
124 #
125 cpu_sequencers.append(cpu_seq)

--- 95 unchanged lines hidden ---