MOESI_hammer.py (8180:d8587c913ccf) | MOESI_hammer.py (8257:7226aebb77b4) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 65 unchanged lines hidden (view full) --- 74 dir_cntrl_nodes = [] 75 dma_cntrl_nodes = [] 76 77 # 78 # Must create the individual controllers before the network to ensure the 79 # controller constructors are called before the network constructor 80 # 81 block_size_bits = int(math.log(options.cacheline_size, 2)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 65 unchanged lines hidden (view full) --- 74 dir_cntrl_nodes = [] 75 dma_cntrl_nodes = [] 76 77 # 78 # Must create the individual controllers before the network to ensure the 79 # controller constructors are called before the network constructor 80 # 81 block_size_bits = int(math.log(options.cacheline_size, 2)) |
82 83 cntrl_count = 0 |
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82 83 for i in xrange(options.num_cpus): 84 # 85 # First create the Ruby objects associated with this cpu 86 # 87 l1i_cache = L1Cache(size = options.l1i_size, 88 assoc = options.l1i_assoc, 89 start_index_bit = block_size_bits) --- 9 unchanged lines hidden (view full) --- 99 dcache = l1d_cache, 100 physMemPort = system.physmem.port, 101 physmem = system.physmem) 102 103 if piobus != None: 104 cpu_seq.pio_port = piobus.port 105 106 l1_cntrl = L1Cache_Controller(version = i, | 84 85 for i in xrange(options.num_cpus): 86 # 87 # First create the Ruby objects associated with this cpu 88 # 89 l1i_cache = L1Cache(size = options.l1i_size, 90 assoc = options.l1i_assoc, 91 start_index_bit = block_size_bits) --- 9 unchanged lines hidden (view full) --- 101 dcache = l1d_cache, 102 physMemPort = system.physmem.port, 103 physmem = system.physmem) 104 105 if piobus != None: 106 cpu_seq.pio_port = piobus.port 107 108 l1_cntrl = L1Cache_Controller(version = i, |
109 cntrl_id = cntrl_count, |
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107 sequencer = cpu_seq, 108 L1IcacheMemory = l1i_cache, 109 L1DcacheMemory = l1d_cache, 110 L2cacheMemory = l2_cache, 111 no_mig_atomic = not \ 112 options.allow_atomic_migration) 113 114 if options.recycle_latency: 115 l1_cntrl.recycle_latency = options.recycle_latency 116 117 exec("system.l1_cntrl%d = l1_cntrl" % i) 118 # 119 # Add controllers and sequencers to the appropriate lists 120 # 121 cpu_sequencers.append(cpu_seq) 122 l1_cntrl_nodes.append(l1_cntrl) 123 | 110 sequencer = cpu_seq, 111 L1IcacheMemory = l1i_cache, 112 L1DcacheMemory = l1d_cache, 113 L2cacheMemory = l2_cache, 114 no_mig_atomic = not \ 115 options.allow_atomic_migration) 116 117 if options.recycle_latency: 118 l1_cntrl.recycle_latency = options.recycle_latency 119 120 exec("system.l1_cntrl%d = l1_cntrl" % i) 121 # 122 # Add controllers and sequencers to the appropriate lists 123 # 124 cpu_sequencers.append(cpu_seq) 125 l1_cntrl_nodes.append(l1_cntrl) 126 |
127 cntrl_count += 1 128 |
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124 phys_mem_size = long(system.physmem.range.second) - \ 125 long(system.physmem.range.first) + 1 126 mem_module_size = phys_mem_size / options.num_dirs 127 128 # 129 # determine size and index bits for probe filter 130 # By default, the probe filter size is configured to be twice the 131 # size of the L2 cache. --- 25 unchanged lines hidden (view full) --- 157 158 dir_size = MemorySize('0B') 159 dir_size.value = mem_module_size 160 161 pf = ProbeFilter(size = pf_size, assoc = 4, 162 start_index_bit = pf_start_bit) 163 164 dir_cntrl = Directory_Controller(version = i, | 129 phys_mem_size = long(system.physmem.range.second) - \ 130 long(system.physmem.range.first) + 1 131 mem_module_size = phys_mem_size / options.num_dirs 132 133 # 134 # determine size and index bits for probe filter 135 # By default, the probe filter size is configured to be twice the 136 # size of the L2 cache. --- 25 unchanged lines hidden (view full) --- 162 163 dir_size = MemorySize('0B') 164 dir_size.value = mem_module_size 165 166 pf = ProbeFilter(size = pf_size, assoc = 4, 167 start_index_bit = pf_start_bit) 168 169 dir_cntrl = Directory_Controller(version = i, |
170 cntrl_id = cntrl_count, |
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165 directory = \ 166 RubyDirectoryMemory( \ 167 version = i, 168 size = dir_size, 169 use_map = options.use_map, 170 map_levels = \ 171 options.map_levels, 172 numa_high_bit = \ --- 4 unchanged lines hidden (view full) --- 177 full_bit_dir_enabled = options.dir_on) 178 179 if options.recycle_latency: 180 dir_cntrl.recycle_latency = options.recycle_latency 181 182 exec("system.dir_cntrl%d = dir_cntrl" % i) 183 dir_cntrl_nodes.append(dir_cntrl) 184 | 171 directory = \ 172 RubyDirectoryMemory( \ 173 version = i, 174 size = dir_size, 175 use_map = options.use_map, 176 map_levels = \ 177 options.map_levels, 178 numa_high_bit = \ --- 4 unchanged lines hidden (view full) --- 183 full_bit_dir_enabled = options.dir_on) 184 185 if options.recycle_latency: 186 dir_cntrl.recycle_latency = options.recycle_latency 187 188 exec("system.dir_cntrl%d = dir_cntrl" % i) 189 dir_cntrl_nodes.append(dir_cntrl) 190 |
191 cntrl_count += 1 192 |
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185 for i, dma_device in enumerate(dma_devices): 186 # 187 # Create the Ruby objects associated with the dma controller 188 # 189 dma_seq = DMASequencer(version = i, 190 physMemPort = system.physmem.port, 191 physmem = system.physmem) 192 193 dma_cntrl = DMA_Controller(version = i, | 193 for i, dma_device in enumerate(dma_devices): 194 # 195 # Create the Ruby objects associated with the dma controller 196 # 197 dma_seq = DMASequencer(version = i, 198 physMemPort = system.physmem.port, 199 physmem = system.physmem) 200 201 dma_cntrl = DMA_Controller(version = i, |
202 cntrl_id = cntrl_count, |
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194 dma_sequencer = dma_seq) 195 196 exec("system.dma_cntrl%d = dma_cntrl" % i) 197 if dma_device.type == 'MemTest': 198 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 199 else: 200 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 201 dma_cntrl_nodes.append(dma_cntrl) 202 203 if options.recycle_latency: 204 dma_cntrl.recycle_latency = options.recycle_latency 205 | 203 dma_sequencer = dma_seq) 204 205 exec("system.dma_cntrl%d = dma_cntrl" % i) 206 if dma_device.type == 'MemTest': 207 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 208 else: 209 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 210 dma_cntrl_nodes.append(dma_cntrl) 211 212 if options.recycle_latency: 213 dma_cntrl.recycle_latency = options.recycle_latency 214 |
215 cntrl_count += 1 216 |
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206 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 207 208 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 217 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 218 219 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |