MOESI_hammer.py (7917:d9afb18a5008) MOESI_hammer.py (8180:d8587c913ccf)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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73 l1_cntrl_nodes = []
74 dir_cntrl_nodes = []
75 dma_cntrl_nodes = []
76
77 #
78 # Must create the individual controllers before the network to ensure the
79 # controller constructors are called before the network constructor
80 #
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 64 unchanged lines hidden (view full) ---

73 l1_cntrl_nodes = []
74 dir_cntrl_nodes = []
75 dma_cntrl_nodes = []
76
77 #
78 # Must create the individual controllers before the network to ensure the
79 # controller constructors are called before the network constructor
80 #
81 block_size_bits = int(math.log(options.cacheline_size, 2))
81
82 for i in xrange(options.num_cpus):
83 #
84 # First create the Ruby objects associated with this cpu
85 #
86 l1i_cache = L1Cache(size = options.l1i_size,
82
83 for i in xrange(options.num_cpus):
84 #
85 # First create the Ruby objects associated with this cpu
86 #
87 l1i_cache = L1Cache(size = options.l1i_size,
87 assoc = options.l1i_assoc)
88 assoc = options.l1i_assoc,
89 start_index_bit = block_size_bits)
88 l1d_cache = L1Cache(size = options.l1d_size,
90 l1d_cache = L1Cache(size = options.l1d_size,
89 assoc = options.l1d_assoc)
91 assoc = options.l1d_assoc,
92 start_index_bit = block_size_bits)
90 l2_cache = L2Cache(size = options.l2_size,
93 l2_cache = L2Cache(size = options.l2_size,
91 assoc = options.l2_assoc)
94 assoc = options.l2_assoc,
95 start_index_bit = block_size_bits)
92
93 cpu_seq = RubySequencer(version = i,
94 icache = l1i_cache,
95 dcache = l1d_cache,
96 physMemPort = system.physmem.port,
97 physmem = system.physmem)
98
99 if piobus != None:

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97 cpu_seq = RubySequencer(version = i,
98 icache = l1i_cache,
99 dcache = l1d_cache,
100 physMemPort = system.physmem.port,
101 physmem = system.physmem)
102
103 if piobus != None:

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