MOESI_hammer.py (7566:6919df046bba) MOESI_hammer.py (7632:acf43d6bbc18)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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181 physMemPort = system.physmem.port,
182 physmem = system.physmem)
183
184 dma_cntrl = DMA_Controller(version = i,
185 dma_sequencer = dma_seq)
186
187 exec("system.dma_cntrl%d = dma_cntrl" % i)
188 if dma_device.type == 'MemTest':
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 172 unchanged lines hidden (view full) ---

181 physMemPort = system.physmem.port,
182 physmem = system.physmem)
183
184 dma_cntrl = DMA_Controller(version = i,
185 dma_sequencer = dma_seq)
186
187 exec("system.dma_cntrl%d = dma_cntrl" % i)
188 if dma_device.type == 'MemTest':
189 system.dma_cntrl.dma_sequencer.port = dma_device.test
189 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
190 else:
190 else:
191 system.dma_cntrl.dma_sequencer.port = dma_device.dma
192 dma_cntrl.dma_sequencer.port = dma_device.dma
191 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
193 dma_cntrl_nodes.append(dma_cntrl)
194
195 if options.recycle_latency:
196 dma_cntrl.recycle_latency = options.recycle_latency
197
198 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
199
200 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
192 dma_cntrl_nodes.append(dma_cntrl)
193
194 if options.recycle_latency:
195 dma_cntrl.recycle_latency = options.recycle_latency
196
197 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
198
199 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)