MOESI_hammer.py (7551:b10ee98aea91) MOESI_hammer.py (7561:02a9a597fce4)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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39
40#
41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 10
45
46def define_options(parser):
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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39
40#
41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 10
45
46def define_options(parser):
47 return
47 parser.add_option("--allow-atomic-migration", action="store_true",
48 help="allow migratory sharing for atomic only accessed blocks")
48
49def create_system(options, system, piobus, dma_devices):
50
51 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
52 panic("This script requires the MOESI_hammer protocol to be built.")
53
54 cpu_sequencers = []
55

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86
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
49
50def create_system(options, system, piobus, dma_devices):
51
52 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
53 panic("This script requires the MOESI_hammer protocol to be built.")
54
55 cpu_sequencers = []
56

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87
88 if piobus != None:
89 cpu_seq.pio_port = piobus.port
90
91 l1_cntrl = L1Cache_Controller(version = i,
92 sequencer = cpu_seq,
93 L1IcacheMemory = l1i_cache,
94 L1DcacheMemory = l1d_cache,
94 L2cacheMemory = l2_cache)
95 L2cacheMemory = l2_cache,
96 no_mig_atomic = not \
97 options.allow_atomic_migration)
95
96 exec("system.l1_cntrl%d = l1_cntrl" % i)
97 #
98 # Add controllers and sequencers to the appropriate lists
99 #
100 cpu_sequencers.append(cpu_seq)
101 l1_cntrl_nodes.append(l1_cntrl)
102

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99 exec("system.l1_cntrl%d = l1_cntrl" % i)
100 #
101 # Add controllers and sequencers to the appropriate lists
102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105

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